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authorHaavard Skinnemoen <hskinnemoen@atmel.com>2007-11-27 13:31:20 +0100
committerHaavard Skinnemoen <hskinnemoen@atmel.com>2007-12-07 14:54:40 +0100
commit8dfe8f29cd371affcc3c6b35658dc4bd95ee7b61 (patch)
treedc1919ab3638bf01694ad8d23745d76046879cf7 /arch/avr32/kernel/entry-avr32b.S
parent320516b78bf197fbf7a38ddab09e9dab75741bae (diff)
downloadtalos-op-linux-8dfe8f29cd371affcc3c6b35658dc4bd95ee7b61.tar.gz
talos-op-linux-8dfe8f29cd371affcc3c6b35658dc4bd95ee7b61.zip
[AVR32] Clean up OCD register usage
Generate a new set of OCD register definitions in asm/ocd.h and rename __mfdr() and __mtdr() to ocd_read() and ocd_write() respectively. The bitfield definitions are a lot more complete now, and they are entirely based on bit numbers, not masks. This is because OCD registers are frequently accessed from assembly code, where bit numbers are a lot more useful (can be fed directly to sbr, bfins, etc.) Bitfields that consist of more than one bit have two definitions: _START, which indicates the number of the first bit, and _SIZE, which indicates the number of bits. These directly correspond to the parameters taken by the bfextu, bfexts and bfins instructions. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32/kernel/entry-avr32b.S')
-rw-r--r--arch/avr32/kernel/entry-avr32b.S14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
index cc2a9b76a344..d7b93f12d8f7 100644
--- a/arch/avr32/kernel/entry-avr32b.S
+++ b/arch/avr32/kernel/entry-avr32b.S
@@ -270,8 +270,8 @@ syscall_exit_work:
lsl r3, 1
sbr r3, 30
sbr r3, 0
- mtdr DBGREG_BWA2A, r2
- mtdr DBGREG_BWC2A, r3
+ mtdr OCD_BWA2A, r2
+ mtdr OCD_BWC2A, r3
rjmp syscall_exit_cont
@@ -521,8 +521,8 @@ fault_exit_work:
lsl r3, 1
sbr r3, 30
sbr r3, 0
- mtdr DBGREG_BWA2A, r2
- mtdr DBGREG_BWC2A, r3
+ mtdr OCD_BWA2A, r2
+ mtdr OCD_BWC2A, r3
rjmp fault_resume_user
/* If we get a debug trap from privileged context we end up here */
@@ -636,9 +636,9 @@ debug_resume_user:
3: bld r1, TIF_SINGLE_STEP
brcc debug_restore_all
- mfdr r2, DBGREG_DC
- sbr r2, DC_SS_BIT
- mtdr DBGREG_DC, r2
+ mfdr r2, OCD_DC
+ sbr r2, OCD_DC_SS_BIT
+ mtdr OCD_DC, r2
rjmp debug_restore_all
.set rsr_int0, SYSREG_RSR_INT0
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