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| author | Sukanto Ghosh <sghosh@apm.com> | 2013-05-14 10:26:54 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2013-05-14 15:44:50 +0100 |
| commit | b4fed0796841b5293b9c9427a5391b7bb20ef2d9 (patch) | |
| tree | 0a17c86e49059cfbec754bc1664fdd2c1692ad50 /arch/arm64/mm/cache.S | |
| parent | c560ecfe9617c629ad09b07edb7523c87b2c9619 (diff) | |
| download | talos-op-linux-b4fed0796841b5293b9c9427a5391b7bb20ef2d9.tar.gz talos-op-linux-b4fed0796841b5293b9c9427a5391b7bb20ef2d9.zip | |
arm64: mm: Fix operands of clz in __flush_dcache_all
The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is
unchanged from ARMv7 architecture and the upper bits are RES0. This
implies that the 'way' field of the operand of 'dc cisw' occupies the
bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands
to 'clz', the existing implementation of __flush_dcache_all is incorrectly
placing the 'way' field in the bit-positions [63 .. (64-A)].
Signed-off-by: Sukanto Ghosh <sghosh@apm.com>
Tested-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'arch/arm64/mm/cache.S')
| -rw-r--r-- | arch/arm64/mm/cache.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index abe69b80cf7f..48a386094fa3 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -52,7 +52,7 @@ loop1: add x2, x2, #4 // add 4 (line length offset) mov x4, #0x3ff and x4, x4, x1, lsr #3 // find maximum number on the way size - clz x5, x4 // find bit position of way size increment + clz w5, w4 // find bit position of way size increment mov x7, #0x7fff and x7, x7, x1, lsr #13 // extract max number of the index size loop2: |
