diff options
| author | Joonyoung Shim <jy0922.shim@samsung.com> | 2012-03-07 04:23:47 -0800 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-03-09 07:31:30 -0800 |
| commit | 99f6e1f50cbb048325c966f2d0e7fe3e47010905 (patch) | |
| tree | b7e108793beb7d40685607a918e15aa2656cd5d0 /arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h | |
| parent | 6cdeddcc8149672d4b888709d063825a80304d09 (diff) | |
| download | talos-op-linux-99f6e1f50cbb048325c966f2d0e7fe3e47010905.tar.gz talos-op-linux-99f6e1f50cbb048325c966f2d0e7fe3e47010905.zip | |
ARM: S3C64XX: Add usb otg phy control
This patch supports to control usb otg phy of S3C64XX. Currently, the
driver for usb otg controls usb otg phy but it can be removed by this
patch.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[Rebased on the newest git/kgene/linux-samsung #for-next]
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Mark Brown<broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h')
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h index a111ad871833..fcf279662067 100644 --- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h @@ -25,8 +25,9 @@ #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) #define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) -#define SRC_PHYPWR_OTG_DISABLE (1 << 4) -#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3) +#define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) +#define S3C_PHYPWR_OTG_DISABLE (1 << 4) +#define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) #define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) #define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) @@ -42,7 +43,7 @@ #define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) #define S3C_RSTCON_PHYCLK (1 << 2) -#define S3C_RSTCON_HCLK (1 << 2) +#define S3C_RSTCON_HCLK (1 << 1) #define S3C_RSTCON_PHY (1 << 0) #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) |
