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| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-09 13:05:57 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-09 13:05:57 -0700 |
| commit | 932c37c375cca25175f9b6acee4c75d7a96d985f (patch) | |
| tree | d7ba3620cd9a7a21c2de1bdfc7badd7637ed635e /arch/arm/mm/proc-macros.S | |
| parent | c855ff3718e5f667b463b20b9de516b4cd7625ad (diff) | |
| parent | 805f53f085346b6765eda02820721a14ce0d644f (diff) | |
| download | talos-op-linux-932c37c375cca25175f9b6acee4c75d7a96d985f.tar.gz talos-op-linux-932c37c375cca25175f9b6acee4c75d7a96d985f.zip | |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits)
ARM: OMAP: Fix GCC-reported compile time bug
ARM: OMAP: restore CONFIG_GENERIC_TIME
ARM: OMAP: partial LED fixes
ARM: OMAP: add SoSSI clock (call propagate_rate for childrens)
ARM: OMAP: FB sync with N800 tree (support for dynamic SRAM allocations)
ARM: OMAP: Sync framebuffer headers with N800 tree
ARM: OMAP: Mostly cosmetic to sync up with linux-omap tree
ARM: OMAP: Fix gpmc header
ARM: OMAP: Add mailbox support for IVA
[ARM] armv7: add Makefile and Kconfig entries
[ARM] armv7: add support for asid-tagged VIVT I-cache
[ARM] armv7: add dedicated ARMv7 barrier instructions
[ARM] armv7: Add ARMv7 cacheid macros
[ARM] armv7: add support for ARMv7 cores.
[ARM] Fix ARM branch relocation range
[ARM] 4363/1: AT91: Remove legacy PIO definitions
[ARM] 4361/1: AT91: Build error
ARM: OMAP: Sync core code with linux-omap
ARM: OMAP: Sync headers with linux-omap
ARM: OMAP: h4 must have blinky leds!!
...
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 9e2c89eb2115..b13150052a76 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -59,3 +59,15 @@ .word \ucset #endif .endm + +/* + * cache_line_size - get the cache line size from the CSIDR register + * (available on ARMv7+). It assumes that the CSSR register was configured + * to access the L1 data cache CSIDR. + */ + .macro dcache_line_size, reg, tmp + mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR + and \tmp, \tmp, #7 @ cache line size encoding + mov \reg, #16 @ size offset + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm |
