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| author | wanzongshun <mcuos.com@gmail.com> | 2009-12-31 15:06:05 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-01-27 22:03:00 +0000 |
| commit | a62e90308f7b6965310cf4ec61393aef6861f50d (patch) | |
| tree | 3370d9bdd43f2f75607ad59f921adafbecf537a7 /arch/arm/mach-nuc93x/include/mach/regs-irq.h | |
| parent | 74d2e4f8d79ae0c4b6ec027958d5b18058662eea (diff) | |
| download | talos-op-linux-a62e90308f7b6965310cf4ec61393aef6861f50d.tar.gz talos-op-linux-a62e90308f7b6965310cf4ec61393aef6861f50d.zip | |
ARM: 5859/1: Add nuc93x platform support
The previous nuc932 support patches have been discarded by me and because it belongs to
another SoCs series named nuc93x,at present, which included nuc931 and nuc932, I think it is
better to create a new mach-nuc93x,So I made the patch,and request your advice.Thanks!
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-nuc93x/include/mach/regs-irq.h')
| -rw-r--r-- | arch/arm/mach-nuc93x/include/mach/regs-irq.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-irq.h b/arch/arm/mach-nuc93x/include/mach/regs-irq.h new file mode 100644 index 000000000000..23021592de51 --- /dev/null +++ b/arch/arm/mach-nuc93x/include/mach/regs-irq.h @@ -0,0 +1,42 @@ +/* + * arch/arm/mach-nuc93x/include/mach/regs-irq.h + * + * Copyright (c) 2008 Nuvoton technology corporation + * All rights reserved. + * + * Wan ZongShun <mcuos.com@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef ___ASM_ARCH_REGS_IRQ_H +#define ___ASM_ARCH_REGS_IRQ_H + +/* Advance Interrupt Controller (AIC) Registers */ + +#define AIC_BA NUC93X_VA_IRQ + +#define REG_AIC_IRQSC (AIC_BA+0x80) +#define REG_AIC_GEN (AIC_BA+0x84) +#define REG_AIC_GASR (AIC_BA+0x88) +#define REG_AIC_GSCR (AIC_BA+0x8C) +#define REG_AIC_IRSR (AIC_BA+0x100) +#define REG_AIC_IASR (AIC_BA+0x104) +#define REG_AIC_ISR (AIC_BA+0x108) +#define REG_AIC_IPER (AIC_BA+0x10C) +#define REG_AIC_ISNR (AIC_BA+0x110) +#define REG_AIC_IMR (AIC_BA+0x114) +#define REG_AIC_OISR (AIC_BA+0x118) +#define REG_AIC_MECR (AIC_BA+0x120) +#define REG_AIC_MDCR (AIC_BA+0x124) +#define REG_AIC_SSCR (AIC_BA+0x128) +#define REG_AIC_SCCR (AIC_BA+0x12C) +#define REG_AIC_EOSCR (AIC_BA+0x130) +#define AIC_IPER (0x10C) +#define AIC_ISNR (0x110) + +#endif /* ___ASM_ARCH_REGS_IRQ_H */ |
