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| author | Dave Airlie <airlied@redhat.com> | 2011-10-18 10:54:30 +0100 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-10-18 10:54:30 +0100 |
| commit | 017ed8012e74ca15748863f45d2c078453026a0a (patch) | |
| tree | 7071171a06de4e93fc890e0afce5c23596a26619 /arch/arm/mach-exynos4/clock.c | |
| parent | 80d9b24a658c83602aea66e45e2347c5bb3cbd47 (diff) | |
| parent | 899e3ee404961a90b828ad527573aaaac39f0ab1 (diff) | |
| download | talos-op-linux-017ed8012e74ca15748863f45d2c078453026a0a.tar.gz talos-op-linux-017ed8012e74ca15748863f45d2c078453026a0a.zip | |
Merge tag 'v3.1-rc10' into drm-core-next
There are a number of fixes in mainline required for code in -next,
also there was a few conflicts I'd rather resolve myself.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Conflicts:
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon_asic.h
Diffstat (limited to 'arch/arm/mach-exynos4/clock.c')
| -rw-r--r-- | arch/arm/mach-exynos4/clock.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 1561b036a9bf..86964d2e9e1b 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -899,8 +899,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, }, { .clk = { - .name = "sclk_cam", - .devname = "exynos4-fimc.0", + .name = "sclk_cam0", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 16), }, @@ -909,8 +908,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, }, { .clk = { - .name = "sclk_cam", - .devname = "exynos4-fimc.1", + .name = "sclk_cam1", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 20), }, @@ -1160,7 +1158,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650); + __raw_readl(S5P_VPLL_CON1), pll_4650c); clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; |
