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| author | Will Deacon <will.deacon@arm.com> | 2013-05-02 13:52:01 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2013-05-30 16:02:33 +0100 |
| commit | e38a517578d6c0f764b0d0f6e26dcdf9f70c69d7 (patch) | |
| tree | 118c5eeced958a227e1cdf77fa365e2881069d3f /arch/arm/include/asm/pgtable-3level.h | |
| parent | 28d4bf7a2929c5e525171d249e12662e21130ec3 (diff) | |
| download | talos-op-linux-e38a517578d6c0f764b0d0f6e26dcdf9f70c69d7.tar.gz talos-op-linux-e38a517578d6c0f764b0d0f6e26dcdf9f70c69d7.zip | |
ARM: lpae: fix definition of PTE_HWTABLE_PTRS
For 2-level page tables, PTE_HWTABLE_PTRS describes the offset between
Linux PTEs and hardware PTEs. On LPAE, there is no distinction (since
we have 64-bit descriptors with plenty of space) so PTE_HWTABLE_PTRS
should be 0. Unfortunately, it is wrongly defined as PTRS_PER_PTE,
meaning that current pte table flushing is off by a page. Luckily,
all current LPAE implementations are SMP, so the hardware walker can
snoop L1.
This patch fixes the broken definition.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/include/asm/pgtable-3level.h')
| -rw-r--r-- | arch/arm/include/asm/pgtable-3level.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 5b85b218b0f0..d03c589cf6b5 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -33,7 +33,7 @@ #define PTRS_PER_PMD 512 #define PTRS_PER_PGD 4 -#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#define PTE_HWTABLE_PTRS (0) #define PTE_HWTABLE_OFF (0) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) |
