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authorTakashi Iwai <tiwai@suse.de>2009-12-25 14:15:31 +0100
committerTakashi Iwai <tiwai@suse.de>2009-12-25 14:15:31 +0100
commit52e04ea89da57274f0313d2bd73ba02f686cfdeb (patch)
tree6ce5d086bcaea4cb534b3fcf6ba736eb48d582a4 /arch/arm/common/dmabounce.c
parent41116e926cb92292fa4fcbe888ae8133fa0038e6 (diff)
parent8b90ca08821fee79e181bfcbc3bbd41ef5637136 (diff)
downloadtalos-op-linux-52e04ea89da57274f0313d2bd73ba02f686cfdeb.tar.gz
talos-op-linux-52e04ea89da57274f0313d2bd73ba02f686cfdeb.zip
Merge branch 'fix/misc' into topic/misc
Diffstat (limited to 'arch/arm/common/dmabounce.c')
-rw-r--r--arch/arm/common/dmabounce.c12
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 5a375e5fef21..cc32c1e54a59 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -308,15 +308,11 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
memcpy(ptr, buf->safe, size);
/*
- * DMA buffers must have the same cache properties
- * as if they were really used for DMA - which means
- * data must be written back to RAM. Note that
- * we don't use dmac_flush_range() here for the
- * bidirectional case because we know the cache
- * lines will be coherent with the data written.
+ * Since we may have written to a page cache page,
+ * we need to ensure that the data will be coherent
+ * with user mappings.
*/
- dmac_clean_range(ptr, ptr + size);
- outer_clean_range(__pa(ptr), __pa(ptr) + size);
+ __cpuc_flush_dcache_area(ptr, size);
}
free_safe_buffer(dev->archdata.dmabounce, buf);
}
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