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| author | Stephen Warren <swarren@nvidia.com> | 2013-01-14 10:09:16 -0700 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 11:24:08 -0700 |
| commit | bb2c1de9ffadc0e1cca1925a89cc04204b247f5b (patch) | |
| tree | 16f54860ec023bce97c945e33199b67082045151 /arch/arm/boot/dts/tegra30.dtsi | |
| parent | 0698ed1986b1f87623b1c1ca0c977c352736897e (diff) | |
| download | talos-op-linux-bb2c1de9ffadc0e1cca1925a89cc04204b247f5b.tar.gz talos-op-linux-bb2c1de9ffadc0e1cca1925a89cc04204b247f5b.zip | |
ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT
This ensures nodes are sorted in order of reg address. This makes it
easier to compare against e.g. the U-Boot device trees, and is simply
consistent and clean.
While we're at it, remove the unit address from the cache-controller
node name, since it's unique without it.
Reported-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30.dtsi | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index e55c99173704..a67fc13ec36d 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -121,15 +121,6 @@ interrupts = <1 13 0xf04>; }; - cache-controller@50043000 { - compatible = "arm,pl310-cache"; - reg = <0x50043000 0x1000>; - arm,data-latency = <6 6 2>; - arm,tag-latency = <5 5 2>; - cache-unified; - cache-level = <2>; - }; - intc: interrupt-controller { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 @@ -138,6 +129,15 @@ #interrupt-cells = <3>; }; + cache-controller { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <6 6 2>; + arm,tag-latency = <5 5 2>; + cache-unified; + cache-level = <2>; + }; + timer@60005000 { compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>; |
