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| author | Vineet Gupta <vgupta@synopsys.com> | 2015-07-29 19:20:58 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-08-04 09:26:31 +0530 |
| commit | f5959cb0c34c5c7f9f387e5d8fe1ec831ccb42ac (patch) | |
| tree | 646f0fc7d94072c3f974caa3b0b6033defc6bbe8 /arch/arc/include | |
| parent | 6de7abfbad1c6a45893a47a17c2ac91b551aa90d (diff) | |
| download | talos-op-linux-f5959cb0c34c5c7f9f387e5d8fe1ec831ccb42ac.tar.gz talos-op-linux-f5959cb0c34c5c7f9f387e5d8fe1ec831ccb42ac.zip | |
Revert "ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock"
Extended testing of quad core configuration revealed that this fix was
insufficient. Specifically LTP open posix shm_op/23-1 would cause the
hardware livelock in llock/scond loop in update_cpu_load_active()
So remove this and make way for a proper workaround
This reverts commit a5c8b52abe677977883655166796f167ef1e0084.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include')
| -rw-r--r-- | arch/arc/include/asm/atomic.h | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h index 03484cb4d16d..20b7dc17979e 100644 --- a/arch/arc/include/asm/atomic.h +++ b/arch/arc/include/asm/atomic.h @@ -23,21 +23,13 @@ #define atomic_set(v, i) (((v)->counter) = (i)) -#ifdef CONFIG_ISA_ARCV2 -#define PREFETCHW " prefetchw [%1] \n" -#else -#define PREFETCHW -#endif - #define ATOMIC_OP(op, c_op, asm_op) \ static inline void atomic_##op(int i, atomic_t *v) \ { \ unsigned int temp; \ \ __asm__ __volatile__( \ - "1: \n" \ - PREFETCHW \ - " llock %0, [%1] \n" \ + "1: llock %0, [%1] \n" \ " " #asm_op " %0, %0, %2 \n" \ " scond %0, [%1] \n" \ " bnz 1b \n" \ @@ -58,9 +50,7 @@ static inline int atomic_##op##_return(int i, atomic_t *v) \ smp_mb(); \ \ __asm__ __volatile__( \ - "1: \n" \ - PREFETCHW \ - " llock %0, [%1] \n" \ + "1: llock %0, [%1] \n" \ " " #asm_op " %0, %0, %2 \n" \ " scond %0, [%1] \n" \ " bnz 1b \n" \ |
