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| author | Lad, Prabhakar <prabhakar.lad@ti.com> | 2012-10-03 12:05:00 +0530 |
|---|---|---|
| committer | Sekhar Nori <nsekhar@ti.com> | 2012-11-19 13:07:39 +0530 |
| commit | e37212aa5df1937bc19c0d0982d216675020a7ca (patch) | |
| tree | 4f597b5c4c2964f8485e257035b78d4f7f509274 | |
| parent | f4a75d2eb7b1e2206094b901be09adb31ba63681 (diff) | |
| download | talos-op-linux-e37212aa5df1937bc19c0d0982d216675020a7ca.tar.gz talos-op-linux-e37212aa5df1937bc19c0d0982d216675020a7ca.zip | |
ARM: davinci: dm644x: fix out range signal for ED
Fix the video clock setting when custom timings are used with
pclock <= 27MHz. Existing video clock selection uses PLL2 mode
which results in a 54MHz clock whereas using the MXI mode results
in a 27MHz clock (which is the one actually desired).
This bug affects the Enhanced Definition (ED) support on DM644x.
Without this patch, out-range signals errors are were observed on
the TV when viewing ED. An out-of-range signal is often caused when
the field rate is above the rate that the television will handle.
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Sekhar Nori <nsekhar@ti.com>
[nsekhar@ti.com: reword commit message based on on-list discussion]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| -rw-r--r-- | arch/arm/mach-davinci/dm644x.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index cd0c8b1e1ecf..14e9947bad6e 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -713,8 +713,7 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type, break; case VPBE_ENC_CUSTOM_TIMINGS: if (pclock <= 27000000) { - v |= DM644X_VPSS_MUXSEL_PLL2_MODE | - DM644X_VPSS_DACCLKEN; + v |= DM644X_VPSS_DACCLKEN; writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL)); } else { /* |
