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| author | Paul Martin <paul.martin@codethink.co.uk> | 2015-03-30 17:00:57 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-01 17:22:14 +0200 |
| commit | b0abf36ffdc2b7efbb74e02b9dad99b40e85ec3b (patch) | |
| tree | a89d188900d1ee4201f7c68865fafadb26471bdf | |
| parent | 11db04c8f3f2353b45848ceda2e6e3440520f7cb (diff) | |
| download | talos-op-linux-b0abf36ffdc2b7efbb74e02b9dad99b40e85ec3b.tar.gz talos-op-linux-b0abf36ffdc2b7efbb74e02b9dad99b40e85ec3b.zip | |
MIPS: Octeon: Set appropriate endianness in L2C registers
Signed-off-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9629/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-platform.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index e1d56f32f784..d113c8ded6e2 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -325,8 +325,14 @@ static void __init octeon_ehci_hw_start(struct device *dev) /* Use 64-bit addressing. */ ehci_ctl.s.ehci_64b_addr_en = 1; ehci_ctl.s.l2c_addr_msb = 0; +#ifdef __BIG_ENDIAN ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ +#else + ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ + ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ + ehci_ctl.s.inv_reg_a2 = 1; +#endif cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64); octeon2_usb_clocks_stop(); @@ -381,8 +387,14 @@ static void __init octeon_ohci_hw_start(struct device *dev) ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0)); ohci_ctl.s.l2c_addr_msb = 0; +#ifdef __BIG_ENDIAN ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */ ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */ +#else + ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */ + ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */ + ohci_ctl.s.inv_reg_a2 = 1; +#endif cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64); octeon2_usb_clocks_stop(); |
