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| author | Jacob Pan <jacob.jun.pan@linux.intel.com> | 2012-02-13 12:59:20 +0000 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-02-23 12:32:05 -0800 |
| commit | 8ed3087280ee8c527b7090887e333761a9c75474 (patch) | |
| tree | 97cafda33176be7cc1309818d01887f805d25f57 | |
| parent | 990a30c50c2bb3c4570aec7c33bedb969d089b7b (diff) | |
| download | talos-op-linux-8ed3087280ee8c527b7090887e333761a9c75474.tar.gz talos-op-linux-8ed3087280ee8c527b7090887e333761a9c75474.zip | |
x86/mrst/pci: v4l/atomisp: treat atomisp as real pci device
ATOMISP on Medfield is a real PCI device which should be handled differently
than the fake PCI devices on south complex. PCI type 1 access is used for
accessing config space this also has other impact such as PM D3 delay. There
shouldn't be any need for reading base address from IUNIT via msg bus.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| -rw-r--r-- | arch/x86/pci/mrst.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c index 89e55485c787..c5e81a4d7c1e 100644 --- a/arch/x86/pci/mrst.c +++ b/arch/x86/pci/mrst.c @@ -148,7 +148,9 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) */ if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE) return 0; - if (bus == 0 && (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(0, 0))) + if (bus == 0 && (devfn == PCI_DEVFN(2, 0) + || devfn == PCI_DEVFN(0, 0) + || devfn == PCI_DEVFN(3, 0))) return 1; return 0; /* langwell on others */ } |
