talos-op-linux/include/asm-i386, branch v2.6.15

[PATCH] Avoid namespace pollution in

2006-01-02T16:38:38+00:00

In commit 3D59121003721a8fad11ee72e646fd9d3076b5679c, the x86 and x86-64 was changed to include for the configurable timer frequency. However, asm/param.h is sometimes used in userland (it is included indirectly from ), so your commit pollutes the userland namespace with tons of CONFIG_FOO macros. This greatly confuses software packages (such as BusyBox) which use CONFIG_FOO macros themselves to control the inclusion of optional features. After a short exchange, Christoph approved this patch Signed-off-by: Linus Torvalds

x86: Fix silly typo in recent fixes

2005-11-17T18:04:31+00:00

The second __const_sigaddset() should have been a sigdelset.. Compile trouble noted by Greg K-H. Signed-off-by: Linus Torvalds

[PATCH] x86: fix sigaddset() inline asm memory constraint

2005-11-17T16:42:26+00:00

Due to incomplete memory constraints, gcc would miscompile code with sigaddset on i386 if sig arg was const. A quote form Jakub to make the issue clear: "You need either __asm__("btsl %1,%0" : "+m"(*set) : "Ir"(_sig-1) : "cc"); or __asm__("btsl %1,%0" : "=m"(*set) : "Ir"(_sig-1), "m"(*set) : "cc"); because the btsl instruction doesn't just set the memory to some value, but needs to read its previous content as well. If you don't tell that fact to GCC, GCC is of course free to optimize as if the asm was just setting the value and not depended on the previous value." Signed-off-by: Linus Torvalds

Merge x86-64 update from Andi

2005-11-15T03:56:02+00:00

[PATCH] x86_64: Reduce number of retries for reset through keyboard controller

2005-11-15T03:55:16+00:00

Old code could retry for 10 seconds worst time. Only try it for one second now. Suggested by Yinghai Lu Cc: Yinghai.Lu@amd.com Signed-off-by: Andi Kleen Signed-off-by: Linus Torvalds

[PATCH] x86-64/i386: Intel HT, Multi core detection fixes

2005-11-15T03:55:16+00:00

Fields obtained through cpuid vector 0x1(ebx[16:23]) and vector 0x4(eax[14:25], eax[26:31]) indicate the maximum values and might not always be the same as what is available and what OS sees. So make sure "siblings" and "cpu cores" values in /proc/cpuinfo reflect the values as seen by OS instead of what cpuid instruction says. This will also fix the buggy BIOS cases (for example where cpuid on a single core cpu says there are "2" siblings, even when HT is disabled in the BIOS. http://bugzilla.kernel.org/show_bug.cgi?id=4359) Signed-off-by: Suresh Siddha Signed-off-by: Andi Kleen Signed-off-by: Linus Torvalds

[PATCH] atomic: inc_not_zero

2005-11-14T02:14:16+00:00

Introduce an atomic_inc_not_zero operation. Make this a special case of atomic_add_unless because lockless pagecache actually wants atomic_inc_not_negativeone due to its offset refcount. Signed-off-by: Nick Piggin Cc: "Paul E. McKenney" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PATCH] atomic: cmpxchg

2005-11-14T02:14:16+00:00

Introduce an atomic_cmpxchg operation. Signed-off-by: Nick Piggin Cc: "Paul E. McKenney" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PATCH] i386: generic cmpxchg

2005-11-14T02:14:15+00:00

- Make cmpxchg generally available on the i386 platform. - Provide emulation of cmpxchg suitable for uniprocessor if built and run on 386. From: Christoph Lameter - Cut down patch and small style changes. Signed-off-by: Nick Piggin Signed-off-by: Christoph Lameter Cc: "Paul E. McKenney" Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PATCH] PCI: Change MSI to use physical delivery mode always

2005-11-11T00:09:18+00:00

MSI hardcoded delivery mode to use logical delivery mode. Recently x86_64 moved to use physical mode addressing to support physflat mode. With this mode enabled noticed that my eth with MSI werent working. msi_address_init() was hardcoded to use logical mode for i386 and x86_64. So when we switch to use physical mode, things stopped working. Since anyway we dont use lowest priority delivery with MSI, its always directed to just a single CPU. Its safe and simpler to use physical mode always, even when we use logical delivery mode for IPI's or other ioapic RTE's. Signed-off-by: Ashok Raj Signed-off-by: Greg Kroah-Hartman