Talos™ II Linux sources for OpenPOWER https://git.raptorcs.com/git/talos-op-linux/atom?h=master 2020-02-04T03:05:24+00:00 2020-02-04T03:05:24+00:00 Randy Dunlap rdunlap@infradead.org 2020-02-04T01:34:55+00:00 urn:sha1:9a8c8b431b21cddb31c43c090ad1678a999e18fa Add #include of <linux/pinctrl/machine.h> to fix build warnings in pinctrl-pxa2xx.c. Fixes these warnings: In file included from ../drivers/pinctrl/pxa/pinctrl-pxa2xx.c:24:0: ../drivers/pinctrl/pxa/../pinctrl-utils.h:36:8: warning: `enum pinctrl_map_type' declared inside parameter list [enabled by default] enum pinctrl_map_type type); ^ ../drivers/pinctrl/pxa/../pinctrl-utils.h:36:8: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] Link: http://lkml.kernel.org/r/0024542e-cba9-8f13-6c18-32d0050a6007@infradead.org Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> 2020-01-29T17:51:36+00:00 Linus Torvalds torvalds@linux-foundation.org 2020-01-29T17:51:36+00:00 urn:sha1:6ba3d7066c71d2103da255df19eb613d299bab15 Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes, nothing too exciting about this. Some changes hit arch/sh and arch/arm but are well isolated and acknowledged by the respective arch maintainers. Core changes: - Dropped the chained IRQ setup callback into GPIOLIB as we got rid of the last users of that in this changeset. New drivers: - New driver for Ingenic X1830. - New driver for Freescale i.MX8MP. Driver enhancements: - Fix all remaining Intel drivers to pass their IRQ chips along with the GPIO chips. - Intel Baytrail allocates its irqchip dynamically. - Intel Lynxpoint is thoroughly rewritten and modernized. - Aspeed AST2600 pin muxing and configuration is much improved. - Qualcomm SC7180 functions are updated and wakeup interrupt map is provided. - A whole slew of Renesas SH-PFC cleanups and improvements. - Fix up the Intel DT bindings to use the generic YAML DT bindings schema (a first user of this)" * tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: madera: Remove extra blank line pinctrl: qcom: Don't lock around irq_set_irq_wake() pinctrl: mvebu: armada-37xx: use use platform api gpio: Drop the chained IRQ handler assign function pinctrl: freescale: Add i.MX8MP pinctrl driver support dt-bindings: imx: Add pinctrl binding doc for i.MX8MP pinctrl: tigerlake: Tiger Lake uses _HID enumeration pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID pinctrl: iproc: Use platform_get_irq_optional() to avoid error message pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema pinctrl: intel: Pass irqchip when adding gpiochip pinctrl: intel: Add GPIO <-> pin mapping ranges via callback pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins pinctrl: sunrisepoint: Add missing Interrupt Status register offset pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers pinctrl: artpec6: fix __iomem on reg in set pinctrl: ingenic: Use devm_platform_ioremap_resource() pinctrl: ingenic: Factorize irq_set_type function pinctrl: ingenic: Remove duplicated ingenic_chip_info structures ... 2020-01-29T17:43:39+00:00 Linus Torvalds torvalds@linux-foundation.org 2020-01-29T17:43:39+00:00 urn:sha1:fa889d85551e0bd962fdefe1cc113f9ba1d04a36 Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v5.6 kernel cycle. This is a pretty calm cycle so far, nothing special going on really. Some more changes will come in from the irqchip and pin control trees. I also deleted an orphan include file for FMC that was dangling since subsystem was removed. Core changes: - Document the usecases for the kernelspace vs userspace handling of GPIOs. - Handle MSI (message signalled interrupts) properly in the core hierarchical irqdomain code. - Fix a rare race condition while initializing the descriptor array. New drivers: - Xylon LogiCVC GPIO driver. - WDC934x GPIO controller driver. Driver improvements: - Implemented suspend/resume in the Tegra driver. - MPC8xx edge detection fixup. - Properly convert ThunderX to use hierarchical irqdomain with GPIOLIB_IRQCHIP on top of the revert of the previous buggy switchover. This time it works (hopefully). Misc: - Drop a FMC remnant file <linux/ipmi-fru.h> - A slew of fixes" * tag 'gpio-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (48 commits) MAINTAINERS: Replace Tien Hock Loh as Altera PIO maintainer gpiolib: hold gpio devices lock until ->descs array is initialised gpio: aspeed-sgpio: fixed typos gpio: mvebu: clear irq in edge cause register before unmask edge irq gpiolib: Lower verbosity when allocating hierarchy irq gpiolib: Remove duplicated function gpio_do_set_config() gpio: Fix the no return statement warning gpio: wcd934x: Add support to wcd934x gpio controller gpiolib: remove set but not used variable 'config' gpio: vx855: fixed a typo gpio: mockup: sort headers alphabetically gpio: mockup: update the license tag gpio: Remove the unused flags gpiolib: Set lockdep class for hierarchical irq domains gpio: thunderx: Switch to GPIOLIB_IRQCHIP gpiolib: Add the support for the msi parent domain gpiolib: Add support for the irqdomain which doesn't use irq_fwspec as arg gpio: Add use guidance documentation dt-bindings: gpio: wcd934x: Add bindings for gpio gpio: altera: change to platform_get_irq_optional to avoid false-positive error ... 2020-01-27T21:03:00+00:00 Linus Torvalds torvalds@linux-foundation.org 2020-01-27T21:03:00+00:00 urn:sha1:6a1000bd27035bba17ede9dc915166276a811edb Pull ioremap updates from Christoph Hellwig: "Remove the ioremap_nocache API (plus wrappers) that are always identical to ioremap" * tag 'ioremap-5.6' of git://git.infradead.org/users/hch/ioremap: remove ioremap_nocache and devm_ioremap_nocache MIPS: define ioremap_nocache to ioremap 2020-01-27T18:30:42+00:00 Linus Torvalds torvalds@linux-foundation.org 2020-01-27T18:30:42+00:00 urn:sha1:9e1af7567b266dc6c3c8fd434ea807b3206bfdc1 Pull MMC updates from Ulf Hansson: "There are no updates for the MEMSTICK subsystem this time. But note that I am also carrying a patch from the pinctrl tree, which has been shared through an immutable branch. Summary: MMC core: - Convert to reasonable timeouts for all CMD6 commands (updates for BKOPS, CACHE_FLUSH and INAND_CMD38_ARG_EXT_CSD) for eMMC - Respect f_max clock rate at card initialization - Add gpiod_toggle_active_low() API - Consolidate slot-gpio code by using gpiod_toggle_active_low() MMC host: - Add pinctrl_select_default_state() API - Consolidate pintctrl code by using pinctrl_select_default_state() - mmci: Support any block sizes for SDIO for some variants - mmci: Enable reset control for stm32_sdmmc - mmc_spi: Toggle SPI_CS_HIGH polarity rather than hard-coding it - renesas_sdhi: Add support for the r8a77961 variant - renesas_sdhi: A few minor improvements - rockchip-dw-mshc: Add support for the rk3308 variant - sdhci: Enable support for external DMA controllers - sdhci: Fixup error path when sending CMD12 - sdhci-brcmstb: Add support for 7216b0 variant - sdhci-brcmstb: Add support for command queuing (CQHCI) - sdhci-brcmstb: Add support for eMMC HS400ES mode - sdhci-msm: Add support for the sc7180 variant - sdhci-msm: Add support for command queuing (CQHCI) - sdhci-of-at91: Add support for the SAM9x60 variant - sdhci-of-at91: Improve support for tunings - sdhci-of-esdhc: A few fixups for some clock related issues - sdhci-omap: Add support for the am335x and the am437x variants - sdhci-omap: Improve support for erase operations - sdhci-omap: Add support for external DMA" * tag 'mmc-v5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (89 commits) mmc: core: Default to generic_cmd6_time as timeout in __mmc_switch() mmc: block: Use generic_cmd6_time when modifying INAND_CMD38_ARG_EXT_CSD mmc: core: Specify timeouts for BKOPS and CACHE_FLUSH for eMMC mmc: sdhci-cadence: remove unneeded 'inline' marker dt-bindings: mmc: rockchip-dw-mshc: add description for rk3308 dt-bindings: mmc: convert rockchip dw-mshc bindings to yaml dt-bindings: mmc: convert synopsys dw-mshc bindings to yaml mmc: sdhci-msm: Add CQHCI support for sdhci-msm mmc: sdhci: Let a vendor driver supply and update ADMA descriptor size mmc: sdhci-of-esdhc: fix serious issue clock is always disabled mmc: sdhci-of-esdhc: fix transfer mode register reading mmc: sdhci-brcmstb: Fix incorrect switch to HS mode mmc: sdhci-brcmstb: Add support for Command Queuing (CQE) mmc: sdhci-brcmstb: Add shutdown callback mmc: sdhci-brcmstb: Fix driver to defer on clk_get defer mmc: sdhci-brcmstb: Add ability to use HS400ES transfer mode dt-bindings: mmc: brcm,sdhci-brcmstb: Add support for 7216b0 mmc: core: limit probe clock frequency to configured f_max mmc: sdhci-milbeaut: Remove redundant platform_get_irq error message mmc: sdhci: fix an issue of mixing different types ... 2020-01-23T23:31:41+00:00 Charles Keepax ckeepax@opensource.cirrus.com 2020-01-22T11:11:50+00:00 urn:sha1:122ce22cb37b087e7e28ebb16044a622b0a22233 Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20200122111150.11033-1-ckeepax@opensource.cirrus.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2020-01-23T23:31:41+00:00 Stephen Boyd swboyd@chromium.org 2020-01-21T18:09:50+00:00 urn:sha1:1d44616e7549d0154c1224a3eee3c407029294dc We don't need to hold the local pinctrl lock here to set irq wake on the summary irq line. Doing so only leads to lockdep warnings instead of protecting us from anything. Remove the locking. WARNING: possible circular locking dependency detected 5.4.11 #2 Tainted: G W ------------------------------------------------------ cat/3083 is trying to acquire lock: ffffff81f4fa58c0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 but task is already holding lock: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&pctrl->lock){-.-.}: _raw_spin_lock_irqsave+0x64/0x80 msm_gpio_irq_ack+0x68/0xf4 __irq_do_set_handler+0xe0/0x180 __irq_set_handler+0x60/0x9c irq_domain_set_info+0x90/0xb4 gpiochip_hierarchy_irq_domain_alloc+0x110/0x200 __irq_domain_alloc_irqs+0x130/0x29c irq_create_fwspec_mapping+0x1f0/0x300 irq_create_of_mapping+0x70/0x98 of_irq_get+0xa4/0xd4 spi_drv_probe+0x4c/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 __device_attach_driver+0x9c/0x110 bus_for_each_drv+0x88/0xd0 __device_attach+0xb0/0x160 device_initial_probe+0x20/0x2c bus_probe_device+0x34/0x94 device_add+0x35c/0x3f0 spi_add_device+0xbc/0x194 of_register_spi_devices+0x2c8/0x408 spi_register_controller+0x57c/0x6fc spi_geni_probe+0x260/0x328 platform_drv_probe+0x90/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 device_driver_attach+0x4c/0x6c __driver_attach+0xcc/0x154 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0x108/0x1fc driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 spi_geni_driver_init+0x1c/0x24 do_one_initcall+0x1a4/0x3e8 do_initcall_level+0xb4/0xcc do_basic_setup+0x30/0x48 kernel_init_freeable+0x124/0x1a8 kernel_init+0x14/0x100 ret_from_fork+0x10/0x18 -> #0 (&irq_desc_lock_class){-.-.}: __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&pctrl->lock); lock(&irq_desc_lock_class); lock(&pctrl->lock); lock(&irq_desc_lock_class); *** DEADLOCK *** 7 locks held by cat/3083: #0: ffffff81f06d1420 (sb_writers#7){.+.+}, at: vfs_write+0xd0/0x1a4 #1: ffffff81c8935680 (&of->mutex){+.+.}, at: kernfs_fop_write+0x12c/0x1fc #2: ffffff81f4c322f0 (kn->count#337){.+.+}, at: kernfs_fop_write+0x134/0x1fc #3: ffffffe89a641d60 (system_transition_mutex){+.+.}, at: pm_suspend+0x108/0x348 #4: ffffff81f190e970 (&dev->mutex){....}, at: __device_suspend+0x168/0x41c #5: ffffff81f183d8c0 (lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 #6: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c stack backtrace: CPU: 4 PID: 3083 Comm: cat Tainted: G W 5.4.11 #2 Hardware name: Google Cheza (rev3+) (DT) Call trace: dump_backtrace+0x0/0x174 show_stack+0x20/0x2c dump_stack+0xc8/0x124 print_circular_bug+0x2ac/0x2c4 check_noncircular+0x1a0/0x1a8 __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc Fixes: 6aced33f4974 ("pinctrl: msm: drop wake_irqs bitmap") Cc: Douglas Anderson <dianders@chromium.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200121180950.36959-1-swboyd@chromium.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2020-01-23T15:06:11+00:00 Peng Fan peng.fan@nxp.com 2019-12-18T12:43:53+00:00 urn:sha1:06e26b75f5e613b400116fdb7ff6206a681ab271 platform_irq_count() and platform_get_irq() is the more generic way (independent of device trees) to determine the count of available interrupts. So use this instead. As platform_irq_count() might return an error code (which of_irq_count doesn't) some additional handling is necessary. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1576672860-14420-1-git-send-email-peng.fan@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2020-01-23T14:49:39+00:00 Anson Huang Anson.Huang@nxp.com 2020-01-15T01:39:07+00:00 urn:sha1:eec6d97d6da400226529f4748fb8998bb69a5bbf Add the pinctrl driver support for i.MX8MP. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1579052348-32167-2-git-send-email-Anson.Huang@nxp.com Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2020-01-23T14:44:29+00:00 Linus Walleij linus.walleij@linaro.org 2020-01-23T14:44:29+00:00 urn:sha1:a1dd4bfb145e88bdc8374a506409f95916bae368 intel-pinctrl for v5.6-1 * Tiger Lake appears to have _HID enumeration, thus driver has been updated * Coffee Lake-S has the same IP as Sunrisepoint, thus ID has been added * Baytrail has got more clean ups and bug fixes, such as direct IRQ handling * Lynxpoint GPIO has been converted to true pin control driver * The common driver now uses IRQ chip enumeration via GPIO chip The following is an automated git shortlog grouped by driver: baytrail: - Replace WARN with dev_info_once when setting direct-irq pin to output - Do not clear IRQ flags on direct-irq enabled pins - Reuse struct intel_pinctrl in the driver - Use local variable to keep device pointer - Keep pointer to struct device instead of its container - Use GPIO direction definitions - Move IRQ valid mask initialization to a dedicated callback - Group GPIO IRQ chip initialization - Allocate IRQ chip dynamic cherryview: - Use GPIO direction definitions intel: - Pass irqchip when adding gpiochip - Add GPIO <-> pin mapping ranges via callback - Share struct intel_pinctrl for wider use - Use GPIO direction definitions lynxpoint: - Update summary in the driver - Switch to pin control API - Add GPIO <-> pin mapping ranges via callback - Implement ->pin_dbg_show() - Add pin control operations - Reuse struct intel_pinctrl in the driver - Add pin control data structures - Implement intel_gpio_get_direction callback - Implement ->irq_ack() callback - Move ownership check to IRQ chip - Move lp_irq_type() closer to IRQ related routines - Move ->remove closer to ->probe() - Extract lp_gpio_acpi_use() for future use - Convert unsigned to unsigned int - Switch to memory mapped IO accessors - Keep pointer to struct device instead of its container - Relax GPIO request rules - Assume 2 bits for mode selector - Use standard pattern for memory allocation - Use %pR to print IO resource - Drop useless assignment - Correct amount of pins - Use raw_spinlock for locking - Move GPIO driver to pin controller folder sunrisepoint: - Add Coffee Lake-S ACPI ID - Add missing Interrupt Status register offset tigerlake: - Tiger Lake uses _HID enumeration