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<title>talos-op-linux/drivers/gpu/host1x/hw/syncpt_hw.c, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/talos-op-linux/atom?h=master</id>
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<updated>2019-05-30T18:29:52+00:00</updated>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201</title>
<updated>2019-05-30T18:29:52+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-28T17:10:04+00:00</published>
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<id>urn:sha1:9952f6918daa4ab5fc81307a9f90e31a4df3b200</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Reviewed-by: Steve Winslow &lt;swinslow@gmail.com&gt;
Reviewed-by: Richard Fontana &lt;rfontana@redhat.com&gt;
Reviewed-by: Alexios Zavras &lt;alexios.zavras@intel.com&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add Tegra194 support</title>
<updated>2018-11-29T16:11:49+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-01-25T12:10:44+00:00</published>
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<id>urn:sha1:ac1bdbf22bebabfee150bb5c33a02c4d0119d185</id>
<content type='text'>
The host1x hardware found on Tegra194 is mostly backwards compatible
with the version found on Tegra186, with the notable exceptions of the
increased number of syncpoints and mlocks. In addition, some rarely
used features such as syncpoint wait bases were dropped and some
registers had to move around to accomodate the increased number of
syncpoints.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Remove wait check support</title>
<updated>2018-05-18T19:50:04+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-05-05T06:45:47+00:00</published>
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<id>urn:sha1:24c94e166dfe89839129b8e0fae208b6af60d6f1</id>
<content type='text'>
The job submission userspace ABI doesn't support this and there are no
plans to implement it, so all of this code is dead and can be removed.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Enable Tegra186 syncpoint protection</title>
<updated>2017-10-20T12:19:52+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-09-28T12:50:39+00:00</published>
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<id>urn:sha1:c3f52220f276504dea5615cc78750ddc9f468389</id>
<content type='text'>
Since Tegra186 the Host1x hardware allows syncpoints to be assigned to
specific channels, preventing any other channels from incrementing
them.

Enable this feature where available and assign syncpoints to channels
when submitting a job. Syncpoints are currently never unassigned from
channels since that would require extra work and is unnecessary with
the current channel allocation model.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix bitshift/mask multipliers</title>
<updated>2017-08-17T15:57:06+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-08-02T09:55:05+00:00</published>
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<id>urn:sha1:4ac45eb8d17c1a998182c302bd023ecb055bd9ee</id>
<content type='text'>
Some parts of Host1x uses BIT_WORD/BIT_MASK/BITS_PER_LONG to calculate
register or field offsets. This worked fine on ARMv7, but now that
BITS_PER_LONG is 64 but our registers are still 32-bit things are
broken.

Fix by replacing..
- BIT_WORD with (x / 32)
- BIT_MASK with BIT(x % 32)
- BITS_PER_LONG with 32

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Whitespace cleanup for readability</title>
<updated>2016-06-23T09:59:30+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-23T09:35:50+00:00</published>
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<id>urn:sha1:0b8070d12ee2ef62e0b07213d843eb508fba966e</id>
<content type='text'>
Insert a number of blank lines in places where they increase readability
of the code. Also collapse various variable declarations to shorten some
functions and finally rewrite some code for readability.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix a couple of checkpatch warnings</title>
<updated>2016-06-23T09:59:28+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-23T09:33:31+00:00</published>
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<id>urn:sha1:6df633d0dc333ffce683f46f2856024479b170b9</id>
<content type='text'>
Fix a couple of occurrences where no blank line was used to separate
variable declarations from code or where block comments were wrongly
formatted.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Consistently use unsigned int for counts</title>
<updated>2016-06-23T09:59:23+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-22T14:44:07+00:00</published>
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<id>urn:sha1:14c95fc896e1d3929abde448fd86c07bdbae56d5</id>
<content type='text'>
The number of channels, syncpoints, bases and mlocks can never be
negative, so use unsigned int instead of int. Also make loop variables
the same type for consistency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Use relative include paths</title>
<updated>2013-10-31T08:55:40+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-10-09T08:32:54+00:00</published>
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<id>urn:sha1:fc3be3e8fc8b3b6e800d6dc8ffb794e9d27ba5d2</id>
<content type='text'>
This is slightly safer than adding -Idrivers/gpu/host1x to cflags-y.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Rework CPU syncpoint increment</title>
<updated>2013-06-22T10:43:55+00:00</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2013-05-29T10:26:08+00:00</published>
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<id>urn:sha1:ebae30b1fbcc2cc991ce705cc82e16d1e5ddbf51</id>
<content type='text'>
This patch merges host1x_syncpt_cpu_incr to host1x_syncpt_incr() as
they are in practise doing the same thing. host1x_syncpt_incr() is
also modified to return error codes. User space interface is modified
accordingly to pass return values.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Acked-By: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
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