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<title>talos-op-linux/drivers/gpu/drm/nouveau, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
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<updated>2020-02-03T11:36:54+00:00</updated>
<entry>
<title>drm/nouveau/kms/gv100-: avoid sending a core update until the first modeset</title>
<updated>2020-02-03T11:36:54+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-02-03T08:37:07+00:00</published>
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<id>urn:sha1:137c4ba7163ad9d5696b9fde78b1c0898a9c115b</id>
<content type='text'>
The OR routing logic in NVKM does not expect to receive supervisor
interrupts until the DD has provided consistent information on the
ORs it's using and the EVO/NVD assembly state to match.

The combination of changing window ownership + core channel update
during display init triggered a situation where we'd disconnect an
OR from the pad it was meant to still be driving on some systems.

Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/kms/gv100-: move window ownership setup into modesetting path</title>
<updated>2020-02-03T11:36:54+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-02-03T08:36:30+00:00</published>
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<id>urn:sha1:5bb88d07948b6779cb783ec0f08b4c1474d592dd</id>
<content type='text'>
For various complicated reasons, we need to avoid sending a core update
method during display init.  Something, which we've been required to do
on GV100 and up because we've been assigning windows to heads there and
the HW is rather picky about when that's allowed.

This moves window assignment into the modesetting path at a point where
it's much safer to send our first update methods to NVDisplay.

Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/disp/gv100-: halt NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR storms</title>
<updated>2020-02-03T11:36:54+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-02-03T06:58:45+00:00</published>
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<id>urn:sha1:58ae5284f663f0856a13bc6caad93a0fe49d7cb4</id>
<content type='text'>
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/fb/gp102-: allow module to load even when scrubber binary is missing</title>
<updated>2020-01-29T05:49:56+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-01-29T01:29:05+00:00</published>
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<id>urn:sha1:c3463aed05abf06bd5ebaac12f2c015db298b98f</id>
<content type='text'>
Without relaxing this requirement, TU10x boards will fail to load without
an updated linux-firmware, and TU11x will completely fail to load because
FW isn't available yet.

Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/acr: return error when registering LSF if ACR not supported</title>
<updated>2020-01-29T05:49:56+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-01-29T01:20:34+00:00</published>
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<id>urn:sha1:1c338ed5e52b62737a9d45f37f085bdbb367821b</id>
<content type='text'>
This fixes an oops on TU11x GPUs where SEC2 attempts to register its falcon,
and triggers a NULL-pointer deref because ACR isn't yet supported.

Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/disp/gv100-: not all channel types support reporting error codes</title>
<updated>2020-01-29T05:49:56+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-01-28T05:03:25+00:00</published>
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<id>urn:sha1:86e18ebd87072ed1ba6ecd86271e7a712115d579</id>
<content type='text'>
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau/disp/nv50-: prevent oops when no channel method map provided</title>
<updated>2020-01-29T05:49:56+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-01-28T04:39:26+00:00</published>
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<id>urn:sha1:0e6176c6d286316e9431b4f695940cfac4ffe6c2</id>
<content type='text'>
The implementations for most channel types contains a map of methods to
priv registers in order to provide debugging info when a disp exception
has been raised.

This info is missing from the implementation of PIO channels as they're
rather simplistic already, however, if an exception is raised by one of
them, we'd end up triggering a NULL-pointer deref.  Not ideal...

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=206299
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau: support synchronous pushbuf submission</title>
<updated>2020-01-29T05:49:56+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-01-23T05:52:12+00:00</published>
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<id>urn:sha1:0352029ed83ff4d3f99e6bcf31bed5a97b07e3cf</id>
<content type='text'>
This is useful for debugging GPU hangs.

Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau: signal pending fences when channel has been killed</title>
<updated>2020-01-29T05:49:47+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-01-23T05:39:27+00:00</published>
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<id>urn:sha1:ea13e5abf807ea912ce84eef6a1946b9a38c6508</id>
<content type='text'>
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
<entry>
<title>drm/nouveau: reject attempts to submit to dead channels</title>
<updated>2020-01-29T05:49:47+00:00</updated>
<author>
<name>Ben Skeggs</name>
<email>bskeggs@redhat.com</email>
</author>
<published>2020-01-23T03:47:12+00:00</published>
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<id>urn:sha1:0181f4bfbdcdfdf8474946bf14fd644727fb8363</id>
<content type='text'>
Signed-off-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
</content>
</entry>
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