talos-op-linux/drivers/gpu/drm/nouveau/nvkm, branch masterTalos™ II Linux sources for OpenPOWERhttps://git.raptorcs.com/git/talos-op-linux/atom?h=master2020-02-03T11:36:54+00:00drm/nouveau/disp/gv100-: halt NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR storms2020-02-03T11:36:54+00:00Ben Skeggsbskeggs@redhat.com2020-02-03T06:58:45+00:00urn:sha1:58ae5284f663f0856a13bc6caad93a0fe49d7cb4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/fb/gp102-: allow module to load even when scrubber binary is missing2020-01-29T05:49:56+00:00Ben Skeggsbskeggs@redhat.com2020-01-29T01:29:05+00:00urn:sha1:c3463aed05abf06bd5ebaac12f2c015db298b98f
Without relaxing this requirement, TU10x boards will fail to load without
an updated linux-firmware, and TU11x will completely fail to load because
FW isn't available yet.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/acr: return error when registering LSF if ACR not supported2020-01-29T05:49:56+00:00Ben Skeggsbskeggs@redhat.com2020-01-29T01:20:34+00:00urn:sha1:1c338ed5e52b62737a9d45f37f085bdbb367821b
This fixes an oops on TU11x GPUs where SEC2 attempts to register its falcon,
and triggers a NULL-pointer deref because ACR isn't yet supported.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/disp/gv100-: not all channel types support reporting error codes2020-01-29T05:49:56+00:00Ben Skeggsbskeggs@redhat.com2020-01-28T05:03:25+00:00urn:sha1:86e18ebd87072ed1ba6ecd86271e7a712115d579
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/disp/nv50-: prevent oops when no channel method map provided2020-01-29T05:49:56+00:00Ben Skeggsbskeggs@redhat.com2020-01-28T04:39:26+00:00urn:sha1:0e6176c6d286316e9431b4f695940cfac4ffe6c2
The implementations for most channel types contains a map of methods to
priv registers in order to provide debugging info when a disp exception
has been raised.
This info is missing from the implementation of PIO channels as they're
rather simplistic already, however, if an exception is raised by one of
them, we'd end up triggering a NULL-pointer deref. Not ideal...
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=206299
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/mmu: fix comptag memory leak2020-01-22T22:56:51+00:00Ben Skeggsbskeggs@redhat.com2020-01-22T22:23:06+00:00urn:sha1:35e4909b6a2b4005ced3c4238da60d926b78fdea
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/gr/gp10b: Use gp100_grctx and gp100_gr_zbc2020-01-22T22:56:51+00:00Thierry Redingtreding@nvidia.com2020-01-15T14:07:56+00:00urn:sha1:90e2e96ea37745ae18a1ff7b322e3321731828e4
gp10b doesn't have all the registers that gp102_gr_zbc wants to access,
which causes IBUS MMIO faults to occur. Avoid this by using the gp100
variants of grctx and gr_zbc.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/pmu/gm20b,gp10b: Fix Falcon bootstrapping2020-01-22T22:56:51+00:00Thierry Redingtreding@nvidia.com2020-01-15T14:06:13+00:00urn:sha1:89b34254bb61d0ad5c701413572cf3d993c9bff8
The low-level Falcon bootstrapping callbacks are expected to return 0 on
success or a negative error code on failure. However, the implementation
on Tegra returns the ID or mask of the Falcons that were bootstrapped on
success, thus breaking the calling code, which treats this as failure.
Fix this by making sure we only return 0 or a negative error code, just
like the code for discrete GPUs does.
Fixes: 86ce2a71539c ("drm/nouveau/flcn/cmdq: move command generation to subdevs")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/gr/tu10x: initial support2020-01-15T00:50:30+00:00Ben Skeggsbskeggs@redhat.com2020-01-14T20:34:22+00:00urn:sha1:afa3b96b058d87c2c44d1c83dadb2ba6998d03ce
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drm/nouveau/acr/tu10x: initial support2020-01-15T00:50:30+00:00Ben Skeggsbskeggs@redhat.com2020-01-14T20:34:22+00:00urn:sha1:3fa8fe1572bc708596318280a22669dfc9eaf805
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>