talos-op-linux/drivers/gpu/drm/nouveau/nvkm/engine, branch master

drm/nouveau/disp/gv100-: halt NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR storms

2020-02-03T11:36:54+00:00

Signed-off-by: Ben Skeggs

drm/nouveau/disp/gv100-: not all channel types support reporting error codes

2020-01-29T05:49:56+00:00

Signed-off-by: Ben Skeggs

drm/nouveau/disp/nv50-: prevent oops when no channel method map provided

2020-01-29T05:49:56+00:00

The implementations for most channel types contains a map of methods to priv registers in order to provide debugging info when a disp exception has been raised. This info is missing from the implementation of PIO channels as they're rather simplistic already, however, if an exception is raised by one of them, we'd end up triggering a NULL-pointer deref. Not ideal... Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=206299 Signed-off-by: Ben Skeggs

drm/nouveau/gr/gp10b: Use gp100_grctx and gp100_gr_zbc

2020-01-22T22:56:51+00:00

gp10b doesn't have all the registers that gp102_gr_zbc wants to access, which causes IBUS MMIO faults to occur. Avoid this by using the gp100 variants of grctx and gr_zbc. Signed-off-by: Thierry Reding Signed-off-by: Ben Skeggs

drm/nouveau/gr/tu10x: initial support

2020-01-15T00:50:30+00:00

Signed-off-by: Ben Skeggs

drm/nouveau/acr/tu10x: initial support

2020-01-15T00:50:30+00:00

Signed-off-by: Ben Skeggs

drm/nouveau/secboot: remove

2020-01-15T00:50:30+00:00

Signed-off-by: Ben Skeggs

drm/nouveau/acr: implement new subdev to replace "secure boot"

2020-01-15T00:50:29+00:00

ACR is responsible for managing the firmware for LS (Low Secure) falcons, this was previously handled in the driver by SECBOOT. This rewrite started from some test code that attempted to replicate the procedure RM uses in order to debug early Turing ACR firmwares that were provided by NVIDIA for development. Compared with SECBOOT, the code is structured into more individual steps, with the aim of making the process easier to follow/debug, whilst making it possible to support newer firmware versions that may have a different binary format or API interface. The HS (High Secure) binary(s) are now booted earlier in device init, to match the behaviour of RM, whereas SECBOOT would delay this until we try to boot the first LS falcon. There's also additional debugging features available, with the intention of making it easier to solve issues during FW/HW bring-up in the future. Signed-off-by: Ben Skeggs

drm/nouveau/secboot: move code to boot LS falcons to subdevs

2020-01-15T00:50:29+00:00

Signed-off-by: Ben Skeggs

drm/nouveau/flcn/msgq: pass explicit message queue pointer to recv()

2020-01-15T00:50:29+00:00

Signed-off-by: Ben Skeggs