talos-op-linux/drivers/gpu/drm/mediatek/mtk_drm_ddp.c, branch master

drm/mediatek: add no_clk into ddp private data

2019-10-09T08:58:13+00:00

Mutex has no clock in some SoC, so add no_clk in private data and get clock according to no_clk. Signed-off-by: CK Hu

drm/mediatek: add mutex sof register offset into ddp private data

2019-10-09T08:58:13+00:00

mutex sof register offset will be private data of ddp Signed-off-by: Yongqiang Niu Signed-off-by: CK Hu

drm/mediatek: add mutex sof into ddp private data

2019-10-09T08:58:13+00:00

mutex sof will be ddp private data Signed-off-by: Yongqiang Niu Signed-off-by: CK Hu

drm/mediatek: add mutex mod register offset into ddp private data

2019-10-09T08:58:12+00:00

mutex mod register offset will be private data of ddp. Signed-off-by: Yongqiang Niu Signed-off-by: CK Hu

drm/mediatek: add mutex mod into ddp private data

2019-10-09T08:58:12+00:00

except mutex mod, mutex mod reg,mutex sof reg, and mutex sof id will be ddp private data Signed-off-by: Yongqiang Niu Signed-off-by: CK Hu

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

2019-05-30T18:26:41+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Kate Stewart Reviewed-by: Richard Fontana Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman

drm/mediatek: implement connection from BLS to DPI0

2018-10-03T03:56:33+00:00

Modify display driver to support connection from BLS to DPI. Signed-off-by: Bibby Hsieh Signed-off-by: CK Hu

drm/mediatek: fix connection from RDMA2 to DSI1

2018-08-27T03:24:37+00:00

This patch fix connection from RDMA2 to DSI1 Signed-off-by: Stu Hsieh Signed-off-by: CK Hu

drm/mediatek: add connection from RDMA2 to DSI0

2018-08-27T03:24:35+00:00

This patch add connection from RDMA2 to DSI0 Signed-off-by: Stu Hsieh Signed-off-by: CK Hu

drm/mediatek: add connection from RDMA1 to DSI0

2018-08-27T03:24:35+00:00

This patch add connection from RDMA1 to DSI0 Signed-off-by: Stu Hsieh Signed-off-by: CK Hu