<feed xmlns='http://www.w3.org/2005/Atom'>
<title>talos-op-linux/drivers/gpu/drm/amd, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/talos-op-linux/atom?h=master</id>
<link rel='self' href='https://git.raptorcs.com/git/talos-op-linux/atom?h=master'/>
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<updated>2020-02-11T20:42:33+00:00</updated>
<entry>
<title>drm/amdgpu:/navi10: use the ODCAP enum to index the caps array</title>
<updated>2020-02-11T20:42:33+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-02-06T19:53:06+00:00</published>
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<id>urn:sha1:e33a8cfda5198fc09554fdd77ba246de42c886bd</id>
<content type='text'>
Rather than the FEATURE_ID flags.  Avoids a possible reading past
the end of the array.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reported-by: Aleksandr Mezin &lt;mezin.alexander@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 5.5.x
</content>
</entry>
<entry>
<title>drm/amdgpu: update smu_v11_0_pptable.h</title>
<updated>2020-02-11T20:41:06+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-02-06T19:46:34+00:00</published>
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<id>urn:sha1:c1d66bc2e531b4ed3a9464b8e87144cc6b2fd63f</id>
<content type='text'>
Update to the latest changes.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 5.5.x
</content>
</entry>
<entry>
<title>drm/amdgpu: correct comment to clear up the confusion</title>
<updated>2020-02-11T20:40:12+00:00</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2020-02-11T04:10:44+00:00</published>
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<id>urn:sha1:a934f9d866598ec777174d449a0dd903ea3db817</id>
<content type='text'>
Former comment looks to be one intended behavior in code,
actually it's not. So correct it.

Suggested-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: DCN2.x Do not program DPPCLK if same value</title>
<updated>2020-02-11T20:39:45+00:00</updated>
<author>
<name>Sung Lee</name>
<email>sung.lee@amd.com</email>
</author>
<published>2020-02-04T20:49:54+00:00</published>
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<id>urn:sha1:8fab6a2faa1eb388b5eaf1ead4394f380a6403be</id>
<content type='text'>
[WHY]
Programming DPPCLK to the same value currently set may cause
underflow while playing video in certain conditions.

[HOW]
Only program DPPCLK if clock is not the same as the
previous value programmed.

Signed-off-by: Sung Lee &lt;sung.lee@amd.com&gt;
Reviewed-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Don't map ATOM_ENABLE to ATOM_INIT</title>
<updated>2020-02-11T20:38:27+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-01-20T19:56:31+00:00</published>
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<id>urn:sha1:1094c34ec53bc147e53f52ed9fe50899ad075632</id>
<content type='text'>
[Why]
In DCN hardware sequencer we do actually call ATOM_INIT correctly per
pipe. The workaround is not necessary for command table offloading.

[How]
Drop the workaround since it's not needed.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Chris Park &lt;Chris.Park@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn2.5: fix warning</title>
<updated>2020-02-11T20:37:22+00:00</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2020-02-07T13:11:00+00:00</published>
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<id>urn:sha1:b5336bfd6fe512521539e3f0f1cf4a5a6a45d380</id>
<content type='text'>
Fix warning during switching to dpg pause mode for
VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: limit GDS clearing workaround in cold boot sequence</title>
<updated>2020-02-11T20:37:02+00:00</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2020-02-09T08:21:09+00:00</published>
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<id>urn:sha1:2cabe0d4cd88f7386e9c5a82236ceda46080a80b</id>
<content type='text'>
GDS clear workaround will cause gfx failure in suspend/resume case.

[   98.679559] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR* late_init of IP block &lt;gfx_v9_0&gt; failed -110
[   98.679561] PM: dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -110
[   98.679562] PM: Device 0000:03:00.0 failed to resume async: error -110

As this workaround is specific to the HW bug of GDS's ECC error
existing in cold boot up, so bypass this workaround in suspend/
resume case after booting up.

Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix amdgpu pmu to use hwc-&gt;config instead of hwc-&gt;conf</title>
<updated>2020-02-11T20:35:54+00:00</updated>
<author>
<name>Jonathan Kim</name>
<email>jonathan.kim@amd.com</email>
</author>
<published>2020-02-06T16:57:11+00:00</published>
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<id>urn:sha1:46d1da733fbc867cd3c3aabec21aeaacd9a41771</id>
<content type='text'>
hwc-&gt;conf was designated specifically for AMD APU IOMMU purposes.  This
could cause problems in performance and/or function since APU IOMMU
implementation is elsewhere.  Also hwc-&gt;conf and hwc-&gt;config are
different members of an anonymous union so hwc-&gt;conf aliases as
hw-&gt;last_tag.

Signed-off-by: Jonathan Kim &lt;Jonathan.Kim@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amdgpu: Prevent build errors regarding soft/hard-float FP ABI tags</title>
<updated>2020-02-11T20:35:22+00:00</updated>
<author>
<name>Daniel Kolesa</name>
<email>daniel@octaforge.org</email>
</author>
<published>2020-02-06T19:14:35+00:00</published>
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<id>urn:sha1:416611d9b6eebaeae58ed26cc7d23131c69126b1</id>
<content type='text'>
On PowerPC, the compiler will tag object files with whether they
use hard or soft float FP ABI and whether they use 64 or 128-bit
long double ABI. On systems with 64-bit long double ABI, a tag
will get emitted whenever a double is used, as on those systems
a long double is the same as a double. This will prevent linkage
as other files are being compiled with hard-float.

On ppc64, this code will never actually get used for the time
being, as the only currently existing hardware using it are the
Renoir APUs. Therefore, until this is testable and can be fixed
properly, at least make sure the build will not fail.

Signed-off-by: Daniel Kolesa &lt;daniel@octaforge.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1</title>
<updated>2020-02-11T20:10:36+00:00</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2020-02-05T14:20:22+00:00</published>
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<id>urn:sha1:f4d0242b7b43977923f778b4cf787425ef05776e</id>
<content type='text'>
Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode
power off issue on instance 1.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
