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<title>talos-op-linux/drivers/gpu/drm/amd/powerplay/inc, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/talos-op-linux/atom?h=master</id>
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<updated>2020-02-11T20:41:06+00:00</updated>
<entry>
<title>drm/amdgpu: update smu_v11_0_pptable.h</title>
<updated>2020-02-11T20:41:06+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-02-06T19:46:34+00:00</published>
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<id>urn:sha1:c1d66bc2e531b4ed3a9464b8e87144cc6b2fd63f</id>
<content type='text'>
Update to the latest changes.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 5.5.x
</content>
</entry>
<entry>
<title>drm/amdgpu/smu_v11_0: Correct behavior of restoring default tables (v2)</title>
<updated>2020-02-04T15:37:51+00:00</updated>
<author>
<name>Matt Coffin</name>
<email>mcoffin13@gmail.com</email>
</author>
<published>2020-01-25T18:04:05+00:00</published>
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<id>urn:sha1:93c5f1f66c6ad4a3b180c1644f74e1b3b4be7864</id>
<content type='text'>
Previously, the syfs functionality for restoring the default powerplay
table was sourcing it's information from the currently-staged powerplay
table.

This patch adds a step to cache the first overdrive table that we see on
boot, so that it can be used later to "restore" the powerplay table

v2: sqaush my original with Matt's fix

Bug: https://gitlab.freedesktop.org/drm/amd/issues/1020
Signed-off-by: Matt Coffin &lt;mcoffin13@gmail.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 5.5.x
</content>
</entry>
<entry>
<title>drm/amd/powerplay: fix navi10 system intermittent reboot issue V2</title>
<updated>2020-02-04T15:37:08+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-01-30T08:46:38+00:00</published>
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<id>urn:sha1:1cf8c930b378016846c88ef0f1444248033326ec</id>
<content type='text'>
This workaround is needed only for Navi10 12 Gbps SKUs.

V2: added SMU firmware version guard

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/powerplay: update SMU12_DRIVER_IF_VERSION to 11</title>
<updated>2020-01-14T15:18:10+00:00</updated>
<author>
<name>Aaron Liu</name>
<email>aaron.liu@amd.com</email>
</author>
<published>2020-01-09T11:26:40+00:00</published>
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<id>urn:sha1:6ca476bab8fd3d1db82626a5aab1bf8ebae996c9</id>
<content type='text'>
This patch updates SMU12_DRIVER_IF_VERSION to 11.

Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: unified VRAM address for driver table interaction with SMU V2</title>
<updated>2020-01-07T17:01:32+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-12-31T02:39:34+00:00</published>
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<id>urn:sha1:ce0d0ec3390c5cf997e4ca43bd2047fa41e77bf1</id>
<content type='text'>
By this, we can avoid to pass in the VRAM address on every table
transferring. That puts extra unnecessary traffics on SMU on
some cases(e.g. polling the amdgpu_pm_info sysfs interface).

V2: document what the driver table is for and how it works

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: cache the watermark settings on system memory</title>
<updated>2020-01-07T17:01:15+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-12-31T02:33:19+00:00</published>
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<id>urn:sha1:9fa1ed5bf628a871be52bb2d84ade8b108db8902</id>
<content type='text'>
So that we do not need to allocate a piece of VRAM for it. This
is a preparation for coming change which unifies the VRAM address
for all driver tables interaction with SMU.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add smu11_driver_if_arcturus.h new OOB members</title>
<updated>2020-01-07T16:58:30+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-01-02T01:41:54+00:00</published>
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<id>urn:sha1:a210d69872cc752e26952253c9b2a40b45b9344a</id>
<content type='text'>
This is to fit the latest SMC firmware and it's backward compatible.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/smu: add helper function smu_get_dpm_level_range() for smu driver</title>
<updated>2020-01-07T16:57:41+00:00</updated>
<author>
<name>Kevin Wang</name>
<email>kevin1.wang@amd.com</email>
</author>
<published>2019-12-26T06:41:22+00:00</published>
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<id>urn:sha1:e4b613e0b27232cf6d31c385493159cabbc78884</id>
<content type='text'>
this function can help smu driver to query dpm level clock range from
smu firmware.

Signed-off-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/smu: make the set_performance_level logic easier to follow</title>
<updated>2020-01-07T16:56:09+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-12-20T21:34:42+00:00</published>
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<id>urn:sha1:337443d0e29054c95879a6a3149b29cc8fbd04df</id>
<content type='text'>
Have every asic provide a callback for this rather than a mix
of generic and asic specific code.

Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: support custom power profile setting</title>
<updated>2020-01-07T16:55:18+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2019-12-17T07:25:56+00:00</published>
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<id>urn:sha1:18d7ab9899d34e6a7f8cb4d17368b7db398323e4</id>
<content type='text'>
Support custom power profile mode settings on Arcturus.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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