talos-op-linux/drivers/gpu/drm/amd/include/asic_reg, branch master

drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus

2020-01-30T22:15:27+00:00

In previous gfx9 parts, S_BARRIER shader instructions are implicitly S_WAITCNT 0 instructions as well. This setting turns off that mechanism in Arcturus and beyond. With this, shaders must follow the ISA guide insofar as putting in explicit S_WAITCNT operations even after an S_BARRIER. v2: Fix patch title to list component Signed-off-by: Joseph Greathouse Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: add EDC counter registers of gc for Arcturus

2020-01-22T21:36:22+00:00

add reg headers to gc includes v2: remove unused registers and fields in this patch set Signed-off-by: Dennis Li Reviewed-by: Guchun Chen Reviewed-by: Tao Zhou Acked-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: update mmhub 9.4.1 header files for Acrturus

2020-01-22T21:35:42+00:00

Add mask & shift definition of MAM_D(0~3)MEM for all mmhub ranges. Signed-off-by: Dennis Li Acked-by: Alex Deucher Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: added support to get mGPU DRAM base

2020-01-22T21:34:07+00:00

resolves issue with RAS error injection in mGPU configuration Reviewed-by: Hawking Zhang Signed-off-by: John Clements Signed-off-by: Alex Deucher

drm/amd/include: Add OCSC registers

2020-01-16T18:41:06+00:00

Add registers for handling Post Gamma Color Blending (OCSC), which is useful for conversion from RGB->YUV for HDMI. Reviewed-by: Leo Li Acked-by: Harry Wentland Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amdgpu: add defines for DF and TCP Hashing

2020-01-14T15:18:41+00:00

On Arcturus, we need TC channel hashing, which is set by the driver, to match DF hashing, which is set by VBIOS. To match these, we plan to query the DF information and then properly set the TC configuration bits to match them. This patch adds the required fields to register definitions in preparation for a future patch which will use them. Signed-off-by: Joseph Greathouse Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file (v2)

2020-01-14T15:18:09+00:00

(v2): Fix preprocessor tag Signed-off-by: Tom St Denis Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: add MCUMC_ADDRT0 offset to ip header file

2020-01-14T15:18:09+00:00

Both are needed on vega20 and arcturus chip. Signed-off-by: Guchun Chen Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus

2019-12-23T19:56:37+00:00

Arcturus has 8 SEs. Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 for EDC GPR _workarounds, Signed-off-by: James Zhu Reviewed-by: Yong Zhao Signed-off-by: Alex Deucher

drm/amdgpu: add perfmons accessible during df c-states

2019-12-23T19:55:53+00:00

During DF C-State, Perfmon counters outside of range 1D700-1D7FF will encounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4] is being added to avoid SLVERR during read since it falls within this range. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4]. Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry after SLVERR. Signed-off-by: Jonathan Kim Acked-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher