<feed xmlns='http://www.w3.org/2005/Atom'>
<title>talos-op-linux/drivers/gpu/drm/amd/display/dc/dcn10, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/talos-op-linux/atom?h=master</id>
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<updated>2020-02-04T15:32:22+00:00</updated>
<entry>
<title>drm/amd/display: Only enable cursor on pipes that need it</title>
<updated>2020-02-04T15:32:22+00:00</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-01-30T18:29:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-op-linux/commit/?id=c6a228be7f440ad5c341b3039f6033d4a8f070a4'/>
<id>urn:sha1:c6a228be7f440ad5c341b3039f6033d4a8f070a4</id>
<content type='text'>
[Why]
In current code we're essentially drawing the cursor on every pipe
that contains it. This only works when the planes have the same
scaling for src to dest rect, otherwise we'll get "double cursor" where
one cursor is incorrectly filtered and offset from the real position.

[How]
Without dedicated cursor planes on DCN we require at least one pipe
that matches the scaling of the current timing.

This is an optimization and workaround for the most common case where
the top-most plane is not scaled but the bottom-most plane is scaled.

Whenever a pipe has a parent pipe in the blending tree whose recout
fully contains the current pipe we can disable the pipe.

This only applies when the pipe is actually visible of course.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable double buffer for OTG_BLANK</title>
<updated>2020-01-16T19:16:27+00:00</updated>
<author>
<name>Alvin Lee</name>
<email>alvin.lee2@amd.com</email>
</author>
<published>2019-12-30T19:29:06+00:00</published>
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<id>urn:sha1:9f21f3792ffb669623cbad8b084f75aa49c98786</id>
<content type='text'>
[Why]
Currently if seamless boot is enabled, we will skip double buffer enable
for OTG_BLANK. However, we need the double buffer enable in order to
block global sync signals when OTG becomes blanked (for PSR). Blocking
global sync signals prevent pipe from requesting data.

[How]
Move tg_init before seamless boot check.

Signed-off-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: make PSR static screen entry within 30 ms</title>
<updated>2020-01-16T19:16:08+00:00</updated>
<author>
<name>Anthony Koo</name>
<email>Anthony.Koo@amd.com</email>
</author>
<published>2019-12-09T22:26:34+00:00</published>
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<id>urn:sha1:5b5abe9526073ccbf3032d27b5864520829cdd9c</id>
<content type='text'>
[Why]
With different refresh rate panels, the PSR entry/exit time is
different since it is dependent on 2 frame entry time today

[How]
Make static screen num frame entry time to be calculated
such that entry time is within 30 ms instead of fixed num
frames.

Signed-off-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add default switch case for DCC</title>
<updated>2020-01-16T19:15:42+00:00</updated>
<author>
<name>Chris Park</name>
<email>Chris.Park@amd.com</email>
</author>
<published>2019-12-20T20:30:05+00:00</published>
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<id>urn:sha1:d905c33a43dc8014e21e2445ae16ee79e562b91f</id>
<content type='text'>
Signed-off-by: Chris Park &lt;Chris.Park@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Reviewed-by: Jordan Lazare &lt;Jordan.Lazare@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix double buffering in dcn2 ICSC</title>
<updated>2020-01-16T19:13:16+00:00</updated>
<author>
<name>Noah Abradjian</name>
<email>noah.abradjian@amd.com</email>
</author>
<published>2019-12-13T14:31:20+00:00</published>
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<id>urn:sha1:d9eb70ae610fea5ff41b9849cc541c8d5f0146db</id>
<content type='text'>
[Why]
When rapidly adjusting video brightness, screen tearing was observed.
This was due to overwritten values in ICSC registers. In dcn10, this issue had been
fixed by implementing double buffering via alternating ICSC modes.
However, the second register set used in dcn1 doesn't exist in dcn2.

[How]
Create new program_input_csc for dcn20.
Use ICSC_B registers instead of COMA registers as second set.

Signed-off-by: Noah Abradjian &lt;noah.abradjian@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: use true, false for bool variable in dcn10_hw_sequencer.c</title>
<updated>2020-01-07T16:56:23+00:00</updated>
<author>
<name>zhengbin</name>
<email>zhengbin13@huawei.com</email>
</author>
<published>2019-12-24T03:27:37+00:00</published>
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<id>urn:sha1:0ee600a7ec3572ac2ed3f43887dc79113eb44f17</id>
<content type='text'>
Fixes coccicheck warning:

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:482:6-14: WARNING: Assignment of 0/1 to bool variable
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:485:2-10: WARNING: Assignment of 0/1 to bool variable

Reported-by: Hulk Robot &lt;hulkci@huawei.com&gt;
Signed-off-by: zhengbin &lt;zhengbin13@huawei.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix missing cursor on some rotated SLS displays</title>
<updated>2019-12-18T21:09:10+00:00</updated>
<author>
<name>Samson Tam</name>
<email>Samson.Tam@amd.com</email>
</author>
<published>2019-12-04T23:35:15+00:00</published>
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<id>urn:sha1:64267454273ac8203aa3f4c0a9ca71193884e862</id>
<content type='text'>
[Why]
Cursor disappears for some SLS displays that are rotated 180
and 270 degrees.  This occurs when there is no pipe split being
done ( ex. 3 or more displays ).  The cursor calculations assume
pipe splitting is done so when it calculates the new cursor
position in hwss.set_cursor_position(), it is out-of-bounds so
it disables the cursor in hubp.set_cursor_position().

[How]
In non pipe split cases, calculate cursor using viewport size
( width or height ) instead of viewport size * 2 ( the two
because pipe splitting divides the rectangle into two ).

Signed-off-by: Samson Tam &lt;Samson.Tam@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove reliance on pipe indexing</title>
<updated>2019-12-18T21:09:09+00:00</updated>
<author>
<name>Noah Abradjian</name>
<email>noah.abradjian@amd.com</email>
</author>
<published>2019-11-29T18:48:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-op-linux/commit/?id=1380c1bf5b9c31baf820ab545bbabf6b39bfdc0d'/>
<id>urn:sha1:1380c1bf5b9c31baf820ab545bbabf6b39bfdc0d</id>
<content type='text'>
[Why]
In certain instances, there was a reliance on pipe indexing being accurate. However, this
assumption fails with harvesting of pipes 1 or 2, which can occur in production B6 parts.
HW hang would occur as a result.

[How]
Use hubp index for mpcc, and do mpc_init for all theoretical pipes (including disabled ones).

Signed-off-by: Noah Abradjian &lt;noah.abradjian@amd.com&gt;
Reviewed-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: check link status before disable stream</title>
<updated>2019-12-18T21:09:09+00:00</updated>
<author>
<name>Paul Hsieh</name>
<email>paul.hsieh@amd.com</email>
</author>
<published>2019-11-28T02:44:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/talos-op-linux/commit/?id=efca090560815fdda03f5403e3f9cae2c8eca301'/>
<id>urn:sha1:efca090560815fdda03f5403e3f9cae2c8eca301</id>
<content type='text'>
[Why]
1. Set second screen only then unplug external monitor
2. Enter to S4 then plug in external monitor
3. Resume from S4, eDP will not turn off when OS set
   second screen only
Sometimes OS will not set eDP power up cause eDP dpms_off
keep true then driver skipp disable stream

[How]
When drvier try to disable stream, add link status condition

Signed-off-by: Paul Hsieh &lt;paul.hsieh@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: update chroma viewport wa</title>
<updated>2019-12-18T21:09:08+00:00</updated>
<author>
<name>Eric Yang</name>
<email>Eric.Yang2@amd.com</email>
</author>
<published>2019-11-18T20:41:19+00:00</published>
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<id>urn:sha1:cf27a6d15d950ed1beb3926469c9eaa6907bbf88</id>
<content type='text'>
[Why]
Need previously implemented chroma vp wa to work for rotation cases.

[How]
Implement rotation specific wa.

Signed-off-by: Eric Yang &lt;Eric.Yang2@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
