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<title>talos-op-linux/arch/xtensa/boot, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/talos-op-linux/atom?h=master</id>
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<updated>2019-11-26T19:33:38+00:00</updated>
<entry>
<title>xtensa: add XIP kernel support</title>
<updated>2019-11-26T19:33:38+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2017-01-04T01:57:51+00:00</published>
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<id>urn:sha1:7af710d988775aadf440222ecbe0c10eecf3eb54</id>
<content type='text'>
XIP (eXecute In Place) kernel image is the image that can be run
directly from ROM, using RAM only for writable data.

XIP xtensa kernel differs from regular xtensa kernel in the following
ways:
- it has exception/IRQ vectors merged into text section. No vectors
  relocation takes place at kernel startup.
- .data/.bss location must be specified in the kernel configuration,
  its content is copied there in the _startup function.
- .init.text is merged with the rest of text and is executed from ROM.
- when MMU is used the virtual address where the kernel will be mapped
  must be specified in the kernel configuration. It may be in the KSEG
  or in the KIO, __pa macro is adjusted to be able to handle both.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: virt: fix PCI IO ports mapping</title>
<updated>2019-10-15T21:29:53+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-10-15T20:52:03+00:00</published>
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<id>urn:sha1:0c401fdf27ba52830c39670dc81cd8379756bd65</id>
<content type='text'>
virt device tree incorrectly uses 0xf0000000 on both sides of PCI IO
ports address space mapping. This results in incorrect port address
assignment in PCI IO BARs and subsequent crash on attempt to access
them. Use 0 as base address in PCI IO ports address space.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: virt: move PCI root complex to KIO range</title>
<updated>2019-09-02T07:09:30+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-09-02T06:55:49+00:00</published>
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<id>urn:sha1:982792f45894878b9ec13df81e6e02209b34cb11</id>
<content type='text'>
Move PCI configuration space, MMIO and memory to the KIO range to free
vmalloc area and use static TLB to access them. Move MMIO to the
beginning of KIO and define PCI_IOBASE as XCHAL_KIO_BYPASS_VADDR to
match it. Reduce number of supported PCI buses to 0x3f so that ECAM
window fits into first 64MB of the KIO. Reduce size of the PCI memory
window to 128MB so that it fits into KIO.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa</title>
<updated>2019-07-16T19:17:07+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-07-16T19:17:07+00:00</published>
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<id>urn:sha1:3e859477a1db52a0435d06a55fdb54f62d69c292</id>
<content type='text'>
Pull Xtensa updates from Max Filippov:

 - clean up PCI support code

 - add defconfig and DTS for the 'virt' board

 - abstract 'entry' and 'retw' uses in xtensa assembly in preparation
   for XEA3/NX pipeline support

 - random small cleanups

* tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa:
  xtensa: virt: add defconfig and DTS
  xtensa: abstract 'entry' and 'retw' in assembly code
  xtensa: One function call less in bootmem_init()
  xtensa: remove arch/xtensa/include/asm/types.h
  xtensa: use generic pcibios_set_master and pcibios_enable_device
  xtensa: drop dead PCI support code
  xtensa/PCI: Remove unused variable
</content>
</entry>
<entry>
<title>xtensa: virt: add defconfig and DTS</title>
<updated>2019-07-08T21:32:06+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-11-06T01:16:21+00:00</published>
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<id>urn:sha1:775f1f7eacede583ec25ed56e58c4483f2b29265</id>
<content type='text'>
Add defconfig and DTS for a virt board. Defconfig enables PCIe host and
a number of virtio devices. DTS routes legacy PCI IRQs to the first four
level-triggered external IRQ lines. CPU core with edge-triggered IRQs
among the first four may need a custom DTS to work correctly.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500</title>
<updated>2019-06-19T15:09:55+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-06-04T08:11:33+00:00</published>
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<id>urn:sha1:d2912cb15bdda8ba4a5dd73396ad62641af2f520</id>
<content type='text'>
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>treewide: prefix header search paths with $(srctree)/</title>
<updated>2019-05-18T02:49:57+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2019-05-13T06:22:16+00:00</published>
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<id>urn:sha1:9cc342f6c4a06ea613ddef1bcaa25409260aec63</id>
<content type='text'>
Currently, the Kbuild core manipulates header search paths in a crazy
way [1].

To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
the search paths in the srctree. Some Makefiles are already written in
that way, but not all. The goal of this work is to make the notation
consistent, and finally get rid of the gross hacks.

Having whitespaces after -I does not matter since commit 48f6e3cf5bc6
("kbuild: do not drop -I without parameter").

[1]: https://patchwork.kernel.org/patch/9632347/

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>xtensa: replace variant/core.h with asm/core.h</title>
<updated>2019-05-07T00:48:55+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-01-02T03:41:55+00:00</published>
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<id>urn:sha1:8f8d5745bb520c76b81abef4a2cb3023d0313bfd</id>
<content type='text'>
Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: rename BUILTIN_DTB to BUILTIN_DTB_SOURCE</title>
<updated>2019-01-26T10:02:16+00:00</updated>
<author>
<name>Corentin Labbe</name>
<email>clabbe@baylibre.com</email>
</author>
<published>2019-01-23T09:49:18+00:00</published>
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<id>urn:sha1:687cffd3450911b1b7449fd6c30f598b35666b41</id>
<content type='text'>
When building some xtensa config, I hit the following warning:
  drivers/staging/mt7621-dts/Kconfig:4:warning: 'BUILTIN_DTB' has wrong type.
  'select' only accept arguments of bool and tristate type

It is due to some arch use BUILTIN_DTB as a flag for the need to builtin
dtb but xtensa use it as a string for which dtb to bulltin.
But for this (which dtb to build), it is better to use
BUILTIN_DTB_SOURCE like other arch do.

Signed-off-by: Corentin Labbe &lt;clabbe@baylibre.com&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: don't use l32r opcode directly</title>
<updated>2018-12-05T20:53:07+00:00</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-12-05T20:48:19+00:00</published>
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<id>urn:sha1:037602705109ec2ab96340bea93ad87daa3ac046</id>
<content type='text'>
xtensa assembler is capable of representing register loads with either
movi + addmi, l32r or const16, depending on the core configuration.
Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let
the assembler relax them.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
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