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<title>talos-op-linux/arch/riscv/mm, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/talos-op-linux/atom?h=master</id>
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<updated>2020-01-23T18:40:06+00:00</updated>
<entry>
<title>riscv: mm: add support for CONFIG_DEBUG_VIRTUAL</title>
<updated>2020-01-23T18:40:06+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2020-01-02T03:12:39+00:00</published>
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<id>urn:sha1:6435f773d81f02193228685a7e3fe65c983c5de0</id>
<content type='text'>
This patch implements CONFIG_DEBUG_VIRTUAL to do additional checks on
virt_to_phys and __pa_symbol calls. virt_to_phys used for linear mapping
check, and __pa_symbol used for kernel symbol check. In current RISC-V,
kernel image maps to linear mapping area. If CONFIG_DEBUG_VIRTUAL is
disable, these two functions calculate the offset on the address feded
directly without any checks.

The result of test_debug_virtual as follows:

[    0.358456] ------------[ cut here ]------------
[    0.358738] virt_to_phys used for non-linear address: (____ptrval____) (0xffffffd000000000)
[    0.359174] WARNING: CPU: 0 PID: 1 at arch/riscv/mm/physaddr.c:16 __virt_to_phys+0x3c/0x50
[    0.359409] Modules linked in:
[    0.359630] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.5.0-rc3-00002-g5133c5c0ca13 #57
[    0.359861] epc: ffffffe000253d1a ra : ffffffe000253d1a sp : ffffffe03aa87da0
[    0.360019]  gp : ffffffe000ae03b0 tp : ffffffe03aa88000 t0 : ffffffe000af2660
[    0.360175]  t1 : 0000000000000064 t2 : 00000000000000b7 s0 : ffffffe03aa87dc0
[    0.360330]  s1 : ffffffd000000000 a0 : 000000000000004f a1 : 0000000000000000
[    0.360492]  a2 : 0000000000000000 a3 : 0000000000000000 a4 : ffffffe000a84358
[    0.360672]  a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000
[    0.360876]  s2 : ffffffe000ae0600 s3 : ffffffe00000fc7c s4 : ffffffe0000224b0
[    0.361067]  s5 : ffffffe000030890 s6 : ffffffe000022470 s7 : 0000000000000008
[    0.361267]  s8 : ffffffe0000002c4 s9 : ffffffe000ae0640 s10: ffffffe000ae0630
[    0.361453]  s11: 0000000000000000 t3 : 0000000000000000 t4 : 000000000001e6d0
[    0.361636]  t5 : ffffffe000ae0a18 t6 : ffffffe000aee54e
[    0.361806] status: 0000000000000120 badaddr: 0000000000000000 cause: 0000000000000003
[    0.362056] ---[ end trace aec0bf78d4978122 ]---
[    0.362404] PA: 0xfffffff080200000 for VA: 0xffffffd000000000
[    0.362607] PA: 0x00000000baddd2d0 for VA: 0xffffffe03abdd2d0

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Tested-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: Add KASAN support</title>
<updated>2020-01-22T21:09:58+00:00</updated>
<author>
<name>Nick Hu</name>
<email>nickhu@andestech.com</email>
</author>
<published>2020-01-06T18:38:32+00:00</published>
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<id>urn:sha1:8ad8b72721d0f07fa02dbe71f901743f9c71c8e6</id>
<content type='text'>
This patch ports the feature Kernel Address SANitizer (KASAN).

Note: The start address of shadow memory is at the beginning of kernel
space, which is 2^64 - (2^39 / 2) in SV39. The size of the kernel space is
2^38 bytes so the size of shadow memory should be 2^38 / 8. Thus, the
shadow memory would not overlap with the fixmap area.

There are currently two limitations in this port,

1. RV64 only: KASAN need large address space for extra shadow memory
region.

2. KASAN can't debug the modules since the modules are allocated in VMALLOC
area. We mapped the shadow memory, which corresponding to VMALLOC area, to
the kasan_early_shadow_page because we don't have enough physical space for
all the shadow memory corresponding to VMALLOC area.

Signed-off-by: Nick Hu &lt;nickhu@andestech.com&gt;
Reported-by: Greentime Hu &lt;green.hu@gmail.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: mm: use __pa_symbol for kernel symbols</title>
<updated>2020-01-03T08:33:34+00:00</updated>
<author>
<name>Zong Li</name>
<email>zong.li@sifive.com</email>
</author>
<published>2020-01-02T03:12:40+00:00</published>
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<id>urn:sha1:ac51e005fe1456a288929a41d71adc6224e912d2</id>
<content type='text'>
__pa_symbol is the marcro that should be used for kernel symbols. It is
also a pre-requisite for DEBUG_VIRTUAL which will do bounds checking.

Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: export flush_icache_all to modules</title>
<updated>2019-12-28T05:51:01+00:00</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2019-12-17T04:07:04+00:00</published>
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<id>urn:sha1:1833e327a5ea1d1f356fbf6ded0760c9ff4b0594</id>
<content type='text'>
This is needed by LKDTM (crash dump test module), it calls
flush_icache_range(), which on RISC-V turns into flush_icache_all(). On
other architectures, the actual implementation is exported, so follow
that precedence and export it here too.

Fixes build of CONFIG_LKDTM that fails with:
ERROR: "flush_icache_all" [drivers/misc/lkdtm/lkdtm.ko] undefined!

Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: move sifive_l2_cache.c to drivers/soc</title>
<updated>2019-12-20T11:40:24+00:00</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2019-11-07T09:20:39+00:00</published>
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<id>urn:sha1:9209fb51896fe0eef8dfac85afe1f357e9265c0d</id>
<content type='text'>
The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management.  It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.

Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Borislav Petkov &lt;bp@suse.de&gt;
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>Merge tag 'riscv/for-v5.5-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux</title>
<updated>2019-12-04T19:07:00+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-12-04T19:07:00+00:00</published>
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<id>urn:sha1:6cdc7f2efc25a6dbddf7c57bb2eee5d6c033d678</id>
<content type='text'>
Pull more RISC-V updates from Paul Walmsley:
 "A few minor RISC-V updates for v5.5-rc1 that arrived late.

  New features:

   - Dump some kernel virtual memory map details to the console if
     CONFIG_DEBUG_VM is enabled

  Other improvements:

   - Enable more debugging options in the primary defconfigs

  Cleanups:

   - Clean up Kconfig indentation"

* tag 'riscv/for-v5.5-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  RISC-V: Add address map dumper
  riscv: defconfigs: enable more debugging options
  riscv: defconfigs: enable debugfs
  riscv: Fix Kconfig indentation
</content>
</entry>
<entry>
<title>Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremap</title>
<updated>2019-11-28T18:57:12+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-11-28T18:57:12+00:00</published>
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<id>urn:sha1:a308a7102215a582fc474375648965bc5692894b</id>
<content type='text'>
Pull generic ioremap support from Christoph Hellwig:
 "This adds the remaining bits for an entirely generic ioremap and
  iounmap to lib/ioremap.c. To facilitate that, it cleans up the giant
  mess of weird ioremap variants we had with no users outside the arch
  code.

  For now just the three newest ports use the code, but there is more
  than a handful others that can be converted without too much work.

  Summary:

   - clean up various obsolete ioremap and iounmap variants

   - add a new generic ioremap implementation and switch csky, nds32 and
     riscv over to it"

* tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremap: (21 commits)
  nds32: use generic ioremap
  csky: use generic ioremap
  csky: remove ioremap_cache
  riscv: use the generic ioremap code
  lib: provide a simple generic ioremap implementation
  sh: remove __iounmap
  nios2: remove __iounmap
  hexagon: remove __iounmap
  m68k: rename __iounmap and mark it static
  arch: rely on asm-generic/io.h for default ioremap_* definitions
  asm-generic: don't provide ioremap for CONFIG_MMU
  asm-generic: ioremap_uc should behave the same with and without MMU
  xtensa: clean up ioremap
  x86: Clean up ioremap()
  parisc: remove __ioremap
  nios2: remove __ioremap
  alpha: remove the unused __ioremap wrapper
  hexagon: clean up ioremap
  ia64: rename ioremap_nocache to ioremap_uc
  unicore32: remove ioremap_cached
  ...
</content>
</entry>
<entry>
<title>Merge branch 'next/misc2' into for-next</title>
<updated>2019-11-23T02:59:17+00:00</updated>
<author>
<name>Paul Walmsley</name>
<email>paul.walmsley@sifive.com</email>
</author>
<published>2019-11-23T02:59:17+00:00</published>
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<id>urn:sha1:8eace9fb39605f0e201223fd34306ba3b53969b7</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge branch 'next/nommu' into for-next</title>
<updated>2019-11-23T02:59:09+00:00</updated>
<author>
<name>Paul Walmsley</name>
<email>paul.walmsley@sifive.com</email>
</author>
<published>2019-11-23T02:59:09+00:00</published>
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<id>urn:sha1:5ba9aa56e6d3e8fddb954c2f818d1ce0525235bb</id>
<content type='text'>
Conflicts:
	arch/riscv/boot/Makefile
	arch/riscv/include/asm/sbi.h
</content>
</entry>
<entry>
<title>Merge branch 'next/misc' into for-next</title>
<updated>2019-11-23T02:58:34+00:00</updated>
<author>
<name>Paul Walmsley</name>
<email>paul.walmsley@sifive.com</email>
</author>
<published>2019-11-23T02:58:34+00:00</published>
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<id>urn:sha1:4a979862dde46b738316014ca4995eae2f428413</id>
<content type='text'>
</content>
</entry>
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