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<title>talos-op-linux/arch/powerpc/boot/dts/fsl, branch master</title>
<subtitle>Talos™ II Linux sources for OpenPOWER</subtitle>
<id>https://git.raptorcs.com/git/talos-op-linux/atom?h=master</id>
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<updated>2020-01-23T20:17:13+00:00</updated>
<entry>
<title>powerpc/fsl/dts: add fsl,erratum-a011043</title>
<updated>2020-01-23T20:17:13+00:00</updated>
<author>
<name>Madalin Bucur</name>
<email>madalin.bucur@oss.nxp.com</email>
</author>
<published>2020-01-22T13:20:28+00:00</published>
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<id>urn:sha1:73d527aef68f7644e59f22ce7f9ac75e7b533aea</id>
<content type='text'>
Add fsl,erratum-a011043 to internal MDIO buses.
Software may get false read error when reading internal
PCS registers through MDIO. As a workaround, all internal
MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.

Signed-off-by: Madalin Bucur &lt;madalin.bucur@oss.nxp.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>powerpc/kmcent2: add ranges to the pci bridges</title>
<updated>2019-11-17T08:01:02+00:00</updated>
<author>
<name>Valentin Longchamp</name>
<email>valentin@longchamp.me</email>
</author>
<published>2019-11-12T19:56:23+00:00</published>
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<id>urn:sha1:a76bea0287ce13d28494b19649d80d8ee5e7b757</id>
<content type='text'>
This removes the warnings about the fact that the 4 pci bridges (i.e.
the 4 pci hosts) don't have any ranges.

Signed-off-by: Valentin Longchamp &lt;valentin@longchamp.me&gt;
Signed-off-by: Scott Wood &lt;oss@buserror.net&gt;
</content>
</entry>
<entry>
<title>powerpc/kmcent2: update the ethernet devices' phy properties</title>
<updated>2019-11-17T07:53:57+00:00</updated>
<author>
<name>Valentin Longchamp</name>
<email>valentin@longchamp.me</email>
</author>
<published>2019-07-14T20:05:01+00:00</published>
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<id>urn:sha1:ea67a5519d61f14517f9ee35b3151f44202c2023</id>
<content type='text'>
Change all phy-connection-type properties to phy-mode that are better
supported by the fman driver.

Use the more readable fixed-link node for the 2 sgmii links.

Change the RGMII link to rgmii-id as the clock delays are added by the
phy.

Signed-off-by: Valentin Longchamp &lt;valentin@longchamp.me&gt;
Acked-by: Madalin Bucur &lt;madalin.bucur@nxp.com&gt;
Signed-off-by: Scott Wood &lt;oss@buserror.net&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152</title>
<updated>2019-05-30T18:26:32+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-27T06:55:01+00:00</published>
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<id>urn:sha1:2874c5fd284268364ece81a7bd936f3c8168e567</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>powerpc/dts/fsl: add crypto node alias for B4</title>
<updated>2019-05-02T16:54:57+00:00</updated>
<author>
<name>Horia Geantă</name>
<email>horia.geanta@nxp.com</email>
</author>
<published>2019-03-20T12:55:16+00:00</published>
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<id>urn:sha1:32eebf96669568014b79b83a03f7895f3ec8c95f</id>
<content type='text'>
crypto node alias is needed by U-boot to identify the node and
perform fix-ups, like adding "fsl,sec-era" property.

Signed-off-by: Horia Geantă &lt;horia.geanta@nxp.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
<entry>
<title>powerpc/dts/fsl: Fix dtc-flagged interrupt errors</title>
<updated>2018-12-22T03:37:05+00:00</updated>
<author>
<name>Scott Wood</name>
<email>oss@buserror.net</email>
</author>
<published>2018-12-22T03:32:51+00:00</published>
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<id>urn:sha1:ccdde478e8445adaa85f30e555de9fab564d742a</id>
<content type='text'>
mpc8641_hpcn was updated to 4-cell interrupt specifiers, but
PCI interrupt-map was not updated.  It was also missing #interrupt-cells
on the outer PCI buses.

p1020rdb-pc was updated to 4-cell interrupt specifiers, but
the ethernet-phy nodes weren't updated.

mpc832x_rdb had an invalid "interrupts = &lt;0&gt;" on the ethernet-phy nodes.
Besides being the wrong number of cells, 0 is not a valid IPIC interrupt
according to ipic.c.  Presumably it was meant to indicate that these
PHYs are not connected to an interrupt.

Signed-off-by: Scott Wood &lt;oss@buserror.net&gt;
</content>
</entry>
<entry>
<title>powerpc/fsl: Use new clockgen binding</title>
<updated>2018-12-22T02:58:34+00:00</updated>
<author>
<name>Scott Wood</name>
<email>oss@buserror.net</email>
</author>
<published>2018-10-31T06:57:35+00:00</published>
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<id>urn:sha1:54877957e95b0e41f472ee3a7e07100d61259de2</id>
<content type='text'>
The driver retains compatibility with old device trees, but we don't
want the old nodes lying around to be copied, or used as a reference
(some of the mux options are incorrect), or even just being clutter.

Signed-off-by: Scott Wood &lt;oss@buserror.net&gt;
Signed-off-by: Tang Yuantian &lt;andy.tang@nxp.com&gt;
[scottwood: removed sysclk node added by Andy]
Signed-off-by: Scott Wood &lt;oss@buserror.net&gt;
</content>
</entry>
<entry>
<title>Merge tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux</title>
<updated>2018-11-02T16:19:35+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-11-02T16:19:35+00:00</published>
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<id>urn:sha1:b69f9e17a57a50bc34d88975afce4425086e525d</id>
<content type='text'>
Pull powerpc fixes from Michael Ellerman:
 "Some things that I missed due to travel, or that came in late.

  Two fixes also going to stable:

   - A revert of a buggy change to the 8xx TLB miss handlers.

   - Our flushing of SPE (Signal Processing Engine) registers on fork
     was broken.

  Other changes:

   - A change to the KVM decrementer emulation to use proper APIs.

   - Some cleanups to the way we do code patching in the 8xx code.

   - Expose the maximum possible memory for the system in
     /proc/powerpc/lparcfg.

   - Merge some updates from Scott: "a couple device tree updates, and a
     fix for a missing prototype warning"

  A few other minor fixes and a handful of fixes for our selftests.

  Thanks to: Aravinda Prasad, Breno Leitao, Camelia Groza, Christophe
  Leroy, Felipe Rechia, Joel Stanley, Naveen N. Rao, Paul Mackerras,
  Scott Wood, Tyrel Datwyler"

* tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (21 commits)
  selftests/powerpc: Fix compilation issue due to asm label
  selftests/powerpc/cache_shape: Fix out-of-tree build
  selftests/powerpc/switch_endian: Fix out-of-tree build
  selftests/powerpc/pmu: Link ebb tests with -no-pie
  selftests/powerpc/signal: Fix out-of-tree build
  selftests/powerpc/ptrace: Fix out-of-tree build
  powerpc/xmon: Relax frame size for clang
  selftests: powerpc: Fix warning for security subdir
  selftests/powerpc: Relax L1d miss targets for rfi_flush test
  powerpc/process: Fix flush_all_to_thread for SPE
  powerpc/pseries: add missing cpumask.h include file
  selftests/powerpc: Fix ptrace tm failure
  KVM: PPC: Use exported tb_to_ns() function in decrementer emulation
  powerpc/pseries: Export maximum memory value
  powerpc/8xx: Use patch_site for perf counters setup
  powerpc/8xx: Use patch_site for memory setup patching
  powerpc/code-patching: Add a helper to get the address of a patch_site
  Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP"
  powerpc/8xx: add missing header in 8xx_mmu.c
  powerpc/8xx: Add DT node for using the SEC engine of the MPC885
  ...
</content>
</entry>
<entry>
<title>powerpc/dts/fsl: t2080rdb: reorder the Cortina PHY XFI lanes</title>
<updated>2018-10-20T23:23:56+00:00</updated>
<author>
<name>Camelia Groza</name>
<email>camelia.groza@nxp.com</email>
</author>
<published>2018-09-20T11:47:01+00:00</published>
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<id>urn:sha1:0400d65501930e6e99848572b3818914c3b94256</id>
<content type='text'>
According to the T2080RDB schematics, for the CS4315 PHY, the XFI 1 lane is
connected to SFP 2 and the XFI 2 lane is connected to SFP 1. Change the
device tree to reflect the correct PHY order and port association.

Signed-off-by: Camelia Groza &lt;camelia.groza@nxp.com&gt;
Signed-off-by: Scott Wood &lt;oss@buserror.net&gt;
</content>
</entry>
<entry>
<title>powerpc: enable building all dtbs</title>
<updated>2018-10-02T14:23:21+00:00</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2018-08-02T21:32:21+00:00</published>
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<id>urn:sha1:27e88af4e94ee853261972aca1a364c4c567123d</id>
<content type='text'>
Enable the 'dtbs' target for powerpc. This allows building all the dts
files in arch/powerpc/boot/dts/ when COMPILE_TEST and OF_ALL_DTBS are
enabled.

Cc: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Cc: Paul Mackerras &lt;paulus@samba.org&gt;
Cc: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
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