talos-op-linux/arch/mips/lantiq, branch masterTalos™ II Linux sources for OpenPOWERhttps://git.raptorcs.com/git/talos-op-linux/atom?h=master2020-01-06T08:45:59+00:00remove ioremap_nocache and devm_ioremap_nocache2020-01-06T08:45:59+00:00Christoph Hellwighch@lst.de2020-01-06T08:43:50+00:00urn:sha1:4bdc0d676a643140bdf17dbf7eafedee3d496a3c
ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver2019-08-24T14:13:22+00:00Martin Blumenstinglmartin.blumenstingl@googlemail.com2019-07-27T12:04:15+00:00urn:sha1:ed90302be64a53d9031c8ce05428c358b16a5d96
The mainline PCIe PHY driver has it's own devicetree node. Update the
clock alias so the mainline driver finds the clocks.
The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
and GRX390.
The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and
GRX390.
The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390.
Lantiq's board support package (called "UGW") names these registers
"PDI".
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: john@phrozen.org
Cc: kishon@ti.com
Cc: ralf@linux-mips.org
Cc: robh+dt@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: hauke@hauke-m.de
Cc: mark.rutland@arm.com
Cc: ms@dev.tdt.de
Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux2019-07-17T16:42:03+00:00Linus Torvaldstorvalds@linux-foundation.org2019-07-17T16:42:03+00:00urn:sha1:fa121bb3fed6313b1f0af23952301e06cf6d32ed
Pull MIPS updates from Paul Burton:
"A light batch this time around but significant improvements for
certain systems:
- Removal of readq & writeq for MIPS32 kernels where they would
simply BUG() anyway, allowing drivers or other code that #ifdefs on
their presence to work properly.
- Improvements for Ingenic JZ4740 systems, including support for the
external memory controller & pinmuxing fixes for qi_lb60/NanoNote
systems.
- Improvements for Lantiq systems, in particular around SMP & IPIs.
- DT updates for ralink/MediaTek MT7628a systems to probe & configure
a bunch more devices.
- Miscellaneous cleanups & build fixes"
* tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
MIPS: fix some more fall through errors in arch/mips
MIPS: perf events: handle switch statement falling through warnings
mips/kprobes: Export kprobe_fault_handler()
MAINTAINERS: Add myself as Ingenic SoCs maintainer
MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node
MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node
MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node
MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes
MIPS: ralink: mt7628a.dtsi: Add pinmux DT node
MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier
MIPS: lantiq: Add SMP support for lantiq interrupt controller
MIPS: lantiq: Shorten register names, remove unused macros
MIPS: lantiq: Fix bitfield masking
MIPS: lantiq: Remove unused macros
MIPS: lantiq: Fix attributes of of_device_id structure
MIPS: lantiq: Change variables to the same type as the source
MIPS: lantiq: Move macro directly to iomem function
mips: Remove q-accessors from non-64bit platforms
FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h
MIPS: configs: Remove useless UEVENT_HELPER_PATH
...
MIPS: lantiq: Add SMP support for lantiq interrupt controller2019-06-24T21:15:04+00:00Petr Cvekpetrcvekcz@gmail.com2019-06-20T21:39:39+00:00urn:sha1:85cf2c37cb407ed05b55b2474b6c0667b190cc83
Some lantiq devices have two ICU controllers. The IRQ signal is routed
to both of them and user can chose which ICU will resend the IRQ to their
respective VPE. The patch adds the support for the second ICU.
The patch changes a register definition of the driver. Instead of an
individual IM, the whole ICU is defined. This will only affects openwrt
patched kernel (vanilla doesn't have additional .dts files).
Also spinlocks has been added, both cores can RMW different bitfields
in the same register. Added affinity set function. The new VPE cpumask
will take into the action at the irq enable.
The functionality was tested on 4.14 openwrt kernel and TP-W9980B modem.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
MIPS: lantiq: Shorten register names, remove unused macros2019-06-24T21:15:04+00:00Petr Cvekpetrcvekcz@gmail.com2019-06-20T21:39:38+00:00urn:sha1:f0dd300101f316fefb19710ae83bcc97a72cdf68
The macros LTQ_ICU_IM1_ISR and LTQ_ICU_OFFSET seems to be unused, remove
them. Allong with that, remove _IM0 substring from the macro names. The
IM (interrupt module) is already defined in IOMEM access and IM0 would be
misleading.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
MIPS: lantiq: Fix bitfield masking2019-06-24T21:15:04+00:00Petr Cvekpetrcvekcz@gmail.com2019-06-20T21:39:37+00:00urn:sha1:ba1bc0fcdeaf3bf583c1517bd2e3e29cf223c969
The modification of EXIN register doesn't clean the bitfield before
the writing of a new value. After a few modifications the bitfield would
accumulate only '1's.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
MIPS: lantiq: Remove unused macros2019-06-24T21:15:04+00:00Petr Cvekpetrcvekcz@gmail.com2019-06-20T21:39:36+00:00urn:sha1:7c6747bc2e3da8abb63f69eb724006ca8276ce2d
The last use of both macros was in 4.11.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
MIPS: lantiq: Fix attributes of of_device_id structure2019-06-24T21:15:03+00:00Petr Cvekpetrcvekcz@gmail.com2019-06-20T21:39:35+00:00urn:sha1:64a95283c3361e42a75fbe24b6390b25b38387b6
According to the checkpatch the driver structure of_device_id requires
to be const and with attribute __initconst. Change it accordingly.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
MIPS: lantiq: Change variables to the same type as the source2019-06-24T21:15:03+00:00Petr Cvekpetrcvekcz@gmail.com2019-06-20T21:39:34+00:00urn:sha1:39588164d3c94c6519f0b826ecd05d7ee3da16c4
A structure irq_data, irq_desc_get_irq() and irq_linear_revmap() use
a different type than defined in the lantiq ICU driver, which is using
signed integers. The substracted result should never be negative nor is
tested for that situation. Change it to unsigned.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com
MIPS: lantiq: Move macro directly to iomem function2019-06-24T21:15:03+00:00Petr Cvekpetrcvekcz@gmail.com2019-06-20T21:39:33+00:00urn:sha1:aa0f58b4666f7662d178905ac45d94914f72d3d4
Using the variable as a temporary holder for the macro of the register
offset value is not necessary. Move it directly to the IOMEM read/write
call.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com