talos-op-linux/arch/mips/include/asm/mach-sibyte, branch master

MIPS: Remove unused R5432_CP0_INTERRUPT_WAR

2019-07-23T21:33:44+00:00

R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and so the workaround is never used. Remove the dead code. Signed-off-by: Paul Burton Cc: linux-mips@vger.kernel.org

MIPS16e2: Provide feature overrides for non-MIPS16 systems

2017-07-11T12:13:06+00:00

Hardcode the absence of the MIPS16e2 ASE for all the systems that do so for the MIPS16 ASE already, providing for code to be optimized away. Signed-off-by: Maciej W. Rozycki Reviewed-by: James Hogan Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16097/ Signed-off-by: Ralf Baechle

MIPS: SB1: Remove support for Pass 1 parts.

2015-07-14T19:47:34+00:00

Pass 1 parts had a number of significant erratas and were only available in small numbers and under NDA. Full support also required the use of a special toolchain that kept branches properly aligned. These workarounds were never upstreamed and the only toolchain known to have them is Montavista's GCC 3.0-based toolchain which completly obsoleted if not useless these days. So now that automated testing has tripped over the user of the -msb1-pass1-workarounds option, rather than fixing it remove support for pass 1 parts. Probably nobody will notice. I seem to own the last know pass 1 board and I haven't noticed another one in the wild in the past decade, at least. Signed-off-by: Ralf Baechle

MIPS: Whitespace cleanup.

2013-02-01T09:00:22+00:00

Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle

MIPS: PMC-Sierra Yosemite: Remove support.

2012-12-13T17:15:30+00:00

Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle

MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.

2012-10-11T09:10:43+00:00

Most supported systems currently hardwire cpu_has_dsp to 0, so we also can disable support for cpu_has_dsp2 resulting in a slightly smaller kernel. Signed-off-by: Ralf Baechle

MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.

2010-04-12T16:26:19+00:00

Previously it was unconditionally used on all Sibyte family SOCs. The M3 bug has to be handled in the TLB exception handler which is extremly performance sensitive, so this modification is expected to deliver around 2-3% performance improvment. This is important as required changes to the M3 workaround will make it more costly. Signed-off-by: Ralf Baechle

MIPS: Move headfiles to new location below arch/mips/include

2008-10-11T15:18:52+00:00

Signed-off-by: Ralf Baechle