Talos™ II Linux sources for OpenPOWER https://git.raptorcs.com/git/talos-op-linux/atom?h=master 2020-02-08T21:58:44+00:00 2020-02-08T21:58:44+00:00 Linus Torvalds torvalds@linux-foundation.org 2020-02-08T21:58:44+00:00 urn:sha1:1afa9c3b7c9bdcb562e2afe9f58cc99d0b071cdc Pull ARM Device-tree updates from Olof Johansson: "New SoCs: - Atmel/Microchip SAM9X60 (ARM926 SoC) - OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants of it with different GPU/media IP configurations. - ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU) - ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500) - Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem) - Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class) New boards: - Allwinner: + Emlid Neutis SoM (H3 variant) + Libre Computer ALL-H3-IT + PineH64 Model B - Amlogic: + Libretech Amlogic GX PC (s905d and s912-based variants) - Atmel/Microchip: + Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1) - Marvell: + Armada 385-based SolidRun Clearfog GTR - NXP: + Gateworks GW59xx boards based on i.MX6/6Q/6QDL + Tolino Shine 3 eBook reader (i.MX6sl) + Embedded Artists COM (i.MX7ULP) + SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems) + Google Coral Edge TPU (i.MX8MQ) - Rockchip: + Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs) + Radxa Rock Pi N10 (RK3399Pro-based) + VMARC RK3399Pro SOM - ST: + Reference boards for stm32mp15 - ST Ericsson: + Samsung Galaxy S III mini (GT-I8190) + HREF520 reference board for DB8520 - TI OMAP: + Gen1 Amazon Echo (OMAP3630-based) - Qualcomm: + Inforce 6640 Single Board Computer (msm8996-based) + SC7180 IDP (SC7180-based)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits) dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera arm64: dts: ti: k3-am65-main Add CAL node arm64: dts: ti: k3-j721e-main: Add McASP nodes arm64: dts: ti: k3-am654-main: Add McASP nodes arm64: dts: ti: k3-j721e: DMA support arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS arm64: dts: ti: k3-am65: DMA support arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss arm64: dts: ti: k3-am65-main: Correct main NAVSS representation ARM: dts: aspeed: rainier: Add UCD90320 power sequencer ARM: dts: aspeed: rainier: Switch PSUs to unknown version arm64: dts: rockchip: Kill off "simple-panel" compatibles ARM: dts: rockchip: Kill off "simple-panel" compatibles arm64: dts: rockchip: rename dwmmc node names to mmc ARM: dts: rockchip: rename dwmmc node names to mmc arm64: dts: exynos: Rename Samsung and Exynos to lowercase arm64: dts: uniphier: add reset-names to NAND controller node ... 2020-01-23T14:48:33+00:00 Anson Huang Anson.Huang@nxp.com 2020-01-15T01:39:06+00:00 urn:sha1:364efd0db7c336c6defc885e077e73e83daca999 Add binding doc for i.MX8MP pinctrl driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1579052348-32167-1-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2020-01-20T06:49:09+00:00 Olof Johansson olof@lixom.net 2020-01-20T06:49:08+00:00 urn:sha1:c14e723e4074ab07d32ed77a5c0f805957df8e1c ASPEED device tree updates for 5.6 - Cleanups for dtc warnings - Ethernet hardware checksum cleanups. A bug in the driver was fixed so machines don't need to specify this anymore. - Misc improvements * tag 'aspeed-5.6-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: ARM: dts: aspeed: rainier: Add UCD90320 power sequencer ARM: dts: aspeed: rainier: Switch PSUs to unknown version ARM: dts: aspeed: Add SD card for Vesnin ARM: dts: aspeed: yamp: Delete no-hw-checksum ARM: dts: aspeed: netbmc: Delete no-hw-checksum ARM: dts: aspeed: AST2400 disables hw checksum ARM: dts: ibm-power9-dual: Add a unit address for OCC nodes ARM: dts: aspeed-g6: Cleanup watchdog unit address ARM: dts: aspeed-g5: Sort LPC child nodes by unit address ARM: dts: aspeed: Add reg hints to syscon children ARM: dts: aspeed: Cleanup lpc-ctrl and snoop regs ARM: dts: witherspoon: Cleanup gpio-keys-polled properties ARM: dts: swift: Cleanup gpio-keys-polled properties ARM: dts: fp5280g2: Cleanup gpio-keys-polled properties ARM: dts: vesnin: Add unit address for memory node ARM: dts: aspeed-g5: Use recommended generic node name for SDMC ARM: dts: aspeed-g5: Move EDAC node to APB dt-bindings: misc: Document reg for aspeed, p2a-ctrl nodes dt-bindings: pinctrl: aspeed: Add reg property as a hint Link: https://lore.kernel.org/r/CACPK8XepSy6D4CNWjSWDDK0p7Dx_rneWne4t4uyy=di5nx3zmA@mail.gmail.com Signed-off-by: Olof Johansson <olof@lixom.net> 2020-01-13T21:33:43+00:00 Linus Walleij linus.walleij@linaro.org 2020-01-13T21:26:29+00:00 urn:sha1:4784adc69a80188d842624ab1519e056a67cc0bd This fixes some problems that caused build errors in the lgm-io schema file: - No "bindings" infix in the schema id - Move the allOf inclusion for pinconf and pinmux nodes into the patternProperties for the -pins node - We want "groups" not "group" to be compulsory for a pinmux node blended with a pin config node. - Fix the generic pinmux-schema to list "groups" rather than "group" for a pinmux node, this might have led to some confusion. This is a first user of the generic schema so a bit of a bumpy road. Cc: Rob Herring <robh+dt@kernel.org> Cc: Rahul Tanwar <rahul.tanwar@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2020-01-06T23:20:42+00:00 Rahul Tanwar rahul.tanwar@linux.intel.com 2019-12-18T06:20:24+00:00 urn:sha1:0434cd276e7265d6db2bc389a021b795ec16fa69 Kernel 5.5 adds generic pin mux & cfg node schema. Update pinctrl bindings for LGM to use these newly added schemas. Also, rename filename to match the compatible string. Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com> Link: https://lore.kernel.org/r/20191218062024.25475-1-rahul.tanwar@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2020-01-06T22:43:52+00:00 周琰杰 (Zhou Yanjie) zhouyanjie@wanyeetech.com 2019-12-15T16:21:03+00:00 urn:sha1:8bc49f4489bb1a4552a10f51bc642286509a9694 Add the pinctrl bindings for the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1576426864-35348-6-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-12-28T23:30:37+00:00 Linus Walleij linus.walleij@linaro.org 2019-12-28T23:30:37+00:00 urn:sha1:e5399ab2c14963457db221f5a59d12a98f998792 Linux 5.5-rc3 2019-12-16T23:35:26+00:00 Andrew Jeffery andrew@aj.id.au 2019-12-03T12:04:02+00:00 urn:sha1:89d6d772f613690eec9540a24b6b0ce60a99540c The pinctrl node sits under a syscon device, and can assume offsets from the base of the syscon based on the compatible. However, for devicetree correctness allow a reg property to be specified, which an associated driver may choose to use to discover associated resources. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> 2019-12-16T08:38:28+00:00 Rajendra Nayak rnayak@codeaurora.org 2019-12-11T05:24:24+00:00 urn:sha1:22440461b19e773fe75b41fc6e3388d2319ff3be Add new qup functions for qup02/04/11 and qup13 wherein multiple functions (for i2c and uart) share the same pin. This allows users to identify which specific qup function for the instance one needs to use for the pin. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/0101016ef36a5c54-2907cf32-2269-4a8c-9447-b086e7c86d98-000000@us-west-2.amazonses.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2019-12-13T08:38:48+00:00 Andrew Jeffery andrew@aj.id.au 2019-12-02T06:14:26+00:00 urn:sha1:6f0ebdf45c0bb74cf004f6e195f31882bfbf058b The AST2600 provides two USB ports (A and B) that expose various host, device and HID functions. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191202061432.3996-2-andrew@aj.id.au Signed-off-by: Linus Walleij <linus.walleij@linaro.org>