blob: 5bf37fb6ae8f0e1d31616fbe4866b4686fe38a0a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/occ_gpe0/core_data.c $ */
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
#include "core_data.h"
#include "ppe42_scom.h"
#include "p9_config.h"
uint32_t get_core_data(uint32_t i_core,
CoreData* o_data)
{
uint32_t rc = 0;
/* uint32_t size = sizeof(CoreData) / 8;
uint64_t* ptr = (uint64_t*)o_data;
uint32_t i = 0;
*/
// Fake Sensor Initialization for testing
o_data->dts.core[0].fields.reading = 0x200+i_core*2;
o_data->dts.core[1].fields.reading = 0x200+i_core*2+1;
o_data->dts.cache.fields.reading = 0x100+i_core;
o_data->dts.core[0].fields.valid = 1;
o_data->dts.core[1].fields.valid = 1;
o_data->dts.cache.fields.valid = 1;
/* TODO RTC 141391 - No simics support to test this yet.
uint32_t coreSelect = CHIPLET_CORE_ID(i_core);
uint32_t quadSelect = CHIPLET_CACHE_ID((i_core / 4));
dts_sensor_result_reg_t scom_data;
rc = getscom(quadSelect,THERM_DTS_RESULT, &(scom_data.value));
if(!rc)
{
// Pick the sensor reading closest to core TODO check this!
// first two cores - use cache dts0
// last two cores - use cache dts1
if(i_core & 0x00000002)
{
o_data->dts.cache.result = scom_data.half_words.reading[1];
}
else
{
o_data->dts.cache.result = scom_data.half_words.reading[0];
}
rc = getscom(coreSelect,THERM_DTS_RESULT, &(scom_data.value));
if(!rc)
{
o_data->dts.core[0].result = scom_data.half_words.reading[0];
o_data->dts.core[1].result = scom_data.half_words.reading[1];
}
}
*/
return rc;
}
|