/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/occ_405/proc/proc_data_control.h $                        */
/*                                                                        */
/* OpenPOWER OnChipController Project                                     */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
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/*     http://www.apache.org/licenses/LICENSE-2.0                         */
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/* distributed under the License is distributed on an "AS IS" BASIS,      */
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/* IBM_PROLOG_END_TAG                                                     */

#ifndef _PROC_DATA_CONTROL_H
#define _PROC_DATA_CONTROL_H

#include <occ_common.h>
#include <ssx.h>
#include "rtls.h"
//#include "gpe_control.h"

// Initialze the structures used by the GPE
void proc_core_data_control_init( void );

// Task that sets the PMCR, PMBR, PMICR
void task_core_data_control( task_t * i_task );

// Function to demonstrate setting Pstates to all cores
void proc_set_pstate_all(Pstate i_pstate);

// Function to demonstrate setting Pstates one core
void proc_set_core_pstate(Pstate i_pstate, uint8_t i_core);

// Sets the Pmin/Pmax clip values for one core
void proc_set_core_bounds(Pstate i_pmin, Pstate i_pmax, uint8_t i_core);
#endif