From adade8c8ef30ed519322674c762d95663009c5d4 Mon Sep 17 00:00:00 2001 From: mbroyles Date: Mon, 3 Aug 2015 14:02:47 -0500 Subject: new ppe dir Change-Id: I43d54c18ac4f3bce90a4f26510e443a55c446bba Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19509 Reviewed-by: William A. Bryan Tested-by: William A. Bryan --- src/ppe/LAYOUT | 16 + src/ppe/hwp/cache/Makefile | 54 + src/ppe/hwp/cache/cachehcdfiles.mk | 65 + src/ppe/hwp/cache/p9_hcd_cache.H | 54 + src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C | 170 ++ src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H | 62 + src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C | 140 ++ src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C | 313 +++ src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.H | 62 + src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C | 282 +++ src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C | 110 + src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_initf.C | 99 + src/ppe/hwp/cache/p9_hcd_cache_initf.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C | 93 + src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_poweron.C | 84 + src/ppe/hwp/cache/p9_hcd_cache_poweron.H | 66 + src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C | 171 ++ src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C | 87 + src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H | 64 + src/ppe/hwp/cache/p9_hcd_cache_runinit.C | 73 + src/ppe/hwp/cache/p9_hcd_cache_runinit.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_scomcust.C | 93 + src/ppe/hwp/cache/p9_hcd_cache_scomcust.H | 62 + src/ppe/hwp/cache/p9_hcd_cache_scominit.C | 130 ++ src/ppe/hwp/cache/p9_hcd_cache_scominit.H | 63 + src/ppe/hwp/cache/p9_hcd_cache_startclocks.C | 275 +++ src/ppe/hwp/cache/p9_hcd_cache_startclocks.H | 63 + src/ppe/hwp/core/Makefile | 54 + src/ppe/hwp/core/corehcdfiles.mk | 65 + src/ppe/hwp/core/p9_hcd_core.H | 54 + src/ppe/hwp/core/p9_hcd_core_arrayinit.C | 156 ++ src/ppe/hwp/core/p9_hcd_core_arrayinit.H | 63 + src/ppe/hwp/core/p9_hcd_core_chiplet_init.C | 136 ++ src/ppe/hwp/core/p9_hcd_core_chiplet_init.H | 63 + src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C | 196 ++ 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+ src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.H | 61 + src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.C | 52 + src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.H | 61 + .../hwp/perv/p9_sbe_nest_gptr_time_repr_initf.C | 52 + .../hwp/perv/p9_sbe_nest_gptr_time_repr_initf.H | 61 + src/ppe/hwp/perv/p9_sbe_nest_initf.C | 52 + src/ppe/hwp/perv/p9_sbe_nest_initf.H | 61 + src/ppe/hwp/perv/p9_sbe_nest_startclocks.C | 52 + src/ppe/hwp/perv/p9_sbe_nest_startclocks.H | 68 + src/ppe/hwp/perv/p9_sbe_npll_initf.C | 52 + src/ppe/hwp/perv/p9_sbe_npll_initf.H | 64 + src/ppe/hwp/perv/p9_sbe_npll_setup.C | 52 + src/ppe/hwp/perv/p9_sbe_npll_setup.H | 73 + src/ppe/hwp/perv/p9_sbe_select_ex.C | 52 + src/ppe/hwp/perv/p9_sbe_select_ex.H | 66 + src/ppe/hwp/perv/p9_sbe_tp_arrayinit.C | 52 + src/ppe/hwp/perv/p9_sbe_tp_arrayinit.H | 63 + src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C | 52 + src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H | 65 + src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.C | 52 + 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+================================================================================ + +sbe/ - FAPI-Lite SBE code to IPL the chip without the core and cache routine. + - May contain some PPE assembler files/functions. + +corecache/ - Core routines will also land in the CME image while cache routine will also land in the STOP GPE image. + - FAPI-Lite Hcode that initializes the core and cache chiplets. +pgpe/ - PState GPE code +ops/ - SBE chipOps -- may be delivered from the FW team but may have some early engineering forms +lib/ - FAPI-Lite Common PPE code routines (startclocks, arrayinit, etc) +pk/ - PPE Kernel + kernel/ - Base kernel + ppe42/ - Emulation function that don't exist in the PPE42 (div64, ppe_scom) +import/ - place for information about what needs to be mirrored into ppe build. \ No newline at end of file diff --git a/src/ppe/hwp/cache/Makefile b/src/ppe/hwp/cache/Makefile new file mode 100644 index 0000000..115a69a --- /dev/null +++ b/src/ppe/hwp/cache/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/cache/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the cache hardware procedure code. See the +# "cachehcdfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/cache +export SUB_OBJDIR = /cache + +include img_defs.mk +include cachehcdfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(CACHE_OBJECTS)) + +libcache.a: cache + $(AR) crs $(OBJDIR)/libcache.a $(OBJDIR)/*.o + +.PHONY: clean cache +cache: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ppe/hwp/cache/cachehcdfiles.mk b/src/ppe/hwp/cache/cachehcdfiles.mk new file mode 100644 index 0000000..28e36e7 --- /dev/null +++ b/src/ppe/hwp/cache/cachehcdfiles.mk @@ -0,0 +1,65 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/cache/cachehcdfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file cachehcdfiles.mk +# +# @brief mk for including cache hcode object files +# +# @page ChangeLogs Change Logs +# @section cachehcdfiles.mk +# @verbatim +# +# +# Change Log ****************************************************************** +# Flag Defect/Feature User Date Description +# ------ -------------- ---------- ------------ ----------- +# +# @endverbatim +# +########################################################################## +# Object Files +########################################################################## + +CACHE-CPP-SOURCES += p9_hcd_cache_arrayinit.C +CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_init.C +CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_reset.C +CACHE-CPP-SOURCES += p9_hcd_cache_dpll_setup.C +CACHE-CPP-SOURCES += p9_hcd_cache_gptr_time_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_occ_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_cache_poweron.C +CACHE-CPP-SOURCES += p9_hcd_cache_ras_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_cache_repair_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_runinit.C +CACHE-CPP-SOURCES += p9_hcd_cache_scomcust.C +CACHE-CPP-SOURCES += p9_hcd_cache_scominit.C +CACHE-CPP-SOURCES += p9_hcd_cache_startclocks.C + +CACHE-C-SOURCES += +CACHE-S-SOURCES += + +CACHE_OBJECTS += $(CACHE-CPP-SOURCES:.C=.o) +CACHE_OBJECTS += $(CACHE-C-SOURCES:.c=.o) +CACHE_OBJECTS += $(CACHE-S-SOURCES:.S=.o) + diff --git a/src/ppe/hwp/cache/p9_hcd_cache.H b/src/ppe/hwp/cache/p9_hcd_cache.H new file mode 100644 index 0000000..6550690 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache.H @@ -0,0 +1,54 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache.H +/// @brief Cache Chiplet Procedure Includes +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_H__ +#define __P9_HCD_CACHE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // __P9_HCD_CACHE_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C new file mode 100644 index 0000000..465b413 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C @@ -0,0 +1,170 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.C +/// @brief EX Initialize arrays +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Use ABIST engine to zero out all arrays +/// Upon completion, scan0 flush all rings +/// except Vital, Repair, GPTR, TIME and DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_arrayinit.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Initialize Cache Arrays +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_arrayinit( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + uint32_t scan; + uint32_t loop; + + // Procedure Prereq : P0 is pointing to the targeted EX chiplet + // submodules: + // seeprom_array_init_module + // ex_scan0 + + FAPI_INF(" : \ + *** Array Init and Scan0 Cleanup for EX Chiplets ***"); + + // SBE Address Base Register Setups + // Setup PRV_BASE_ADDR1; points to selected EX chiplet + // - mr P1, P0 + FAPI_INF(" : \ + Copy selected EX info from P0 to P1"); + + // Step 1: Array Init for selected EX chiplet + // ARRAY INIT module -> see p9_sbe_tp_array_init.S + // + // At entry: + // + // P1 : The chiplet ID/Multicast Group + // D1 : Clock Regions for Array Init + // + // At exit: + // + // P0, D0, D1, CTR : destroyed + // P1, A0, A1 : maintained + // + FAPI_INF(" : \ + Calling Array Init Subroutine"); + + // >>> IPL/Winkle + // \bug Need to exclude DPLL ring for IPL + // li D1, SCAN_ALLREGIONEXVITAL + // = li D1, SCAN_CLK_ALLEXDPLL + scan = SCAN_CLK_ALLEXDPLL; + + // Execute the array init + // = bsr seeprom_array_init_module + seeprom_array_init_module(scan); + + // Restore P0 with selected EX chiplet info + // - mr P0, P1 + FAPI_INF(" : \ + Copy selected EX info back from P1 to P0"); + + // Step 2: Scan0 for selected EX chiplet except PRV, GPTR, TIME and DPLL + FAPI_INF(" : \ + Calling Scan0 Subroutine"); + + // taken from p9_sbe_ex_chiplet_init + + // >>> IPL/Winkle scan flush - all except vital + + // Hook to bypass in Sim + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Init: Scan0 Module executed: \ + Scan all except vital, DPL, GPTR, and TIME scan chains"); + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + + // \bug remove DPLL ring + // ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALL + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL + // = .endr + for(loop=0;loop : \ + *** End of Procedure ***"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H new file mode 100644 index 0000000..530c4db --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.H +/// @brief EX Initialize arrays +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_ARRAYINIT_H__ +#define __P9_HCD_CACHE_ARRAYINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_arrayinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_arrayinit_FP_t) ( + const fapi2::Target&); + +/// @brief EX Initialize arrays +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_arrayinit( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_ARRAYINIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C new file mode 100644 index 0000000..a73ad42 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C @@ -0,0 +1,140 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.C +/// @brief EX Flush/Initialize +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Scan0 flush all configured chiplet rings except Vital, GPTR, TIME and DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_chiplet_init.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +//#define SIM_PLL +//#define SIM_SPEEDUP +////#define SCAN0_DISABLE +//#define STEP_CHIPLET_INIT_0 0x0 // Resetting DPLL +//#define STEP_CHIPLET_INIT_1 0x1 // Core+ECO glmux switch (IPL/Winkle) +//#define STEP_CHIPLET_INIT_2 0x2 // Core glmux switch (Sleep) +//#define STEP_CHIPLET_INIT_3 0x3 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_4 0x4 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_5 0x5 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_6 0x6 // Before Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_7 0x7 // After Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_8 0x8 // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_9 0x9 // After Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_A 0xA // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_B 0xB // After Core Func flush for Sleep +//#define PORE_REFCLK_CYCLES 1 // \todo need real value for hdw +//#define DPLL_LOCK_DELAY 8192*PORE_REFCLK_CYCLES + +//----------------------------------------------------------------------------- +// Procedure: EX Flush/Initialize +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_chiplet_init( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + uint32_t loop; + + // Procedure Prereq: + // p9_sbe_ex_chiplet_reset, p9_sbe_ex_dpll_initf, p9_sbe_ex_pll_initf + + FAPI_INF(": Entering procedure"); + + // Look for PSCOM error on any chip, fail if we find one + // scan0 flush all configured chiplet rings except EX DPLL + // call ex_scan0_module( ) + + // >>> IPL/Winkle scan flush - all except vital + + // Hook to bypass in Sim + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Init: Scan0 Module executed: \ + Scan all except vital, DPL, GPTR, and TIME scan chains"); + // - updatestep STEP_CHIPLET_INIT_6, D0, P1 + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL + // = .endr + for(loop=0;loop: Exiting procedure"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H new file mode 100644 index 0000000..8dfacbc --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.H +/// @brief EX Flush/Initialize +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_CHIPLET_INIT_H__ +#define __P9_HCD_CACHE_CHIPLET_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_chiplet_init_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_init_FP_t) ( + const fapi2::Target&); + + +/// @brief EX Flush/Initialize +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_chiplet_init( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_CHIPLET_INIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C new file mode 100644 index 0000000..a4fa4ce --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -0,0 +1,313 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_reset.C +/// @brief Cache Chiplet Reset +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Reset quad chiplet logic +/// Scan0 flush entire cache chiplet +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_chiplet_reset.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +// GP3 Bits +// 1 - PCB_EP_RESET +// 2 - GLMMUX Reset +// 3 - PLL_TEST Enable +// 4 - PLLRST - PLL Reset +// 5 - PLL Bypass +// 11 - D_MODE for Vital +// 13 - MPW2 for Vital +// 14 - PMW1 for Vital +// 18 - FENCE_EN for chiplet +// 22 - Resonant Clock disable +// 23:24 - Glitchless Mux Sel +// 25: - ?? (set because System Pervasive flow does this) +// Background: system pervasive as the following setting in their tests: +// 7C1623C000000000 +// Bits set: +// 1, 2, 3, 4, 5, 11, 13, 14, 18, 22, 23, 24, 25 +//#define GP3_INIT_VECTOR (BITS(1,5)|BIT(11)|BIT(13)|BIT(14)|BIT(18)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) + +// hang counter inits +//#define HANG_P1_INIT 0x0400000000000000 +//#define PCB_SL_ERROR_REG_RESET 0xFFFFFFFFFFFFFFFF +//#define STEP_CHIPLET_RESET_1 0x1 // After start of vital clocks +//#define STEP_CHIPLET_RESET_2 0x2 // After fence drop +//#define STEP_CHIPLET_RESET_3 0x3 // Before GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_4 0x4 // After GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_5 0x5 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_6 0x6 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_7 0x7 // Before GPTR flush for Sleep +//#define STEP_CHIPLET_RESET_8 0x8 // After GPTR flush for Sleep + +//------------------------------------------------------------------------------ +// Procedure: Cache Chiplet Reset +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_chiplet_reset( + const fapi2::Target& i_target) +{ + +#if 0 + uint32_t loop; + + ///////////////////////////////////////////////////////////////// + // repeat some init steps of chiplet_init + ///////////////////////////////////////////////////////////////// + + // If there is a unused, powered-off EX chiplet which needs to be + // configured in the following steps to setup the PCB endpoint. + + // Skip the PCB endpoint config steps for sleep so that fences don't + // get dropped (eg by dropping chiplet_enable (GP3(0)). + + FAPI_INF(": \ + Repeat dedicated pervasive init steps for EX "); + + FAPI_DBG(": \ + Reset GP3 for EX chiplet, step needed for hotplug"); + // = sti GENERIC_GP3_0x000F0012,P0,GP3_INIT_VECTOR + FAPI_TRY(putScom(i_target, GENERIC_GP3_0x000F0012, + fapi2:buffer(23452345))); + + FAPI_DBG(": \ + Drop aync reset to Glitchless Mux"); + // = sti GENERIC_GP3_AND_0x000F0013,P0,~BIT(2) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer().flush<1>().clearBit<2>())); + + // 19:21 PM_PI_DECODE needs to be 010 for functional operation(set bit 20) + FAPI_DBG(": \ + Put DPLL in functional mode"); + // = sti GENERIC_GP3_OR_0x000F0014,P0, BIT(20) + FAPI_TRY(putScom(i_target, GENERIC_GP3_OR_0x000F0014, + fapi2::buffer().setBit<20>())); + + // - updatestep STEP_CHIPLET_RESET_1, D0, P1 + + FAPI_DBG(": \ + Release endpoint reset for PCB"); + // = sti GENERIC_GP3_AND_0x000F0013,P0,~BIT(1) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer().flush<1>().clearBit<1>())); + + FAPI_DBG(": \ + Partial good setting"); + // = sti GENERIC_GP3_OR_0x000F0014,P0,BIT(0) + FAPI_TRY(putScom(i_target, GENERIC_GP3_OR_0x000F0014, + fapi2::buffer().setBit<0>())); + + FAPI_DBG(": \ + PCB slave error reg reset"); + // = sti MASTER_PCB_ERR_0x000F001F,P0,PCB_SL_ERROR_REG_RESET + FAPI_TRY(putScom(i_target, MASTER_PCB_ERR_0x000F001F, + fapi2:buffer(643564))); + + FAPI_DBG("Use timer mode for DPLL lock when enabled"); + // = sti EX_PMGP0_OR_0x100F0102, P0, BIT(7) + FAPI_TRY(putScom(i_target, EX_PMGP0_OR_0x100F0102, + fapi2::buffer().setBit<7>())); + + // Set the DPLL Timer value for waiting on DPLL HOLDs in 35:36 + // 00 = 1024 cycles <---- + // 01 = 512 cycles + // 10 = 256 cycles + // 11 = 128 cycles + FAPI_DBG("Set the timer value for waiting on DPLL THOLDs"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(35)|BIT(36)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().insertFromRight<35,2>(0))); + + // Only perform the disablement of PCBS-PM for the IPL work-around when + // doing IPL (eg skip if winkle; this whole section is skipped for sleep) + // >>> IPL + // FAPI_DBG("Disable the PCBS-PM as part of winkle enablement"); + // = sti EX_PMGP0_OR_0x100F0102, P0, BIT(0) + FAPI_TRY(putScom(i_target, EX_PMGP0_OR_0x100F0102, + fapi2:buffer().setBit<0>())); + + // The following is performed for both IPL/Winkle and Sleep + + // Note: These are executed for sleep as well as these fences will have + // already been dropped + + FAPI_DBG(": \ + Remove pervasive ECO fence;"); + // ECO Fence in 22 + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(22)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().clearBit<22>())); + + FAPI_DBG(": \ + Remove winkle mode before scan0 on EX chiplets is executed"); + // PM Exit States: WINKLE_EXIT_DROP_ELEC_FENCE + + FAPI_DBG(": \ + Remove logical pervasive/pcbs-pm fence"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(39)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().clearBit<39>())); + + FAPI_DBG(": \ + Remove PB Winkle Electrical Fence GP3(27)"); + // = sti EX_GP3_AND_0x100F0013,P0,~(BIT(27)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer().flush<1>().clearBit<27>())); + + FAPI_DBG(": \ + Configuring chiplet hang counters") ; + // = sti EX_HANG_P1_0x100F0021,P0,HANG_P1_INIT + data = 34654; // HANG_P1_INIT + FAPI_TRY(putScom(i_target, EX_HANG_P1_0x100F0021, + fapi2:buffer(34654))); + // - updatestep STEP_CHIPLET_RESET_2, D0, P1 + + ////////////////////////////////////////////////////////////// + // perform scan0 module for pervasive chiplet (GPTR_TIME_REPR) + ////////////////////////////////////////////////////////////// + + // >>> IPL/Winkle scan flush - core and EX + + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF01 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + // \todo WORKAROUND UNTIL LOGIC CHANGES + // Drop the core2cache and cache2core fences to allow for L2 scanning + FAPI_DBG(": \ + Remove pervasive ECO fence;"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(20) | BIT(21)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().insertFromRight<20,2>(0))); + + FAPI_DBG("EX Reset: Scan0 Module executed: \ + Scan the GPTR/TIME/REP rings"); + // - updatestep STEP_CHIPLET_RESET_3, D0, P1 + + // = .rept P9_SCAN0_GPTR_REPEAT + // = ex_scan0 SCAN_GPTR_TIME_REP, SCAN_CLK_ALL + // = .endr + for(loop=0;loop +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_CHIPLET_RESET_H__ +#define __P9_HCD_CACHE_CHIPLET_RESET_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_chiplet_reset_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_reset_FP_t) ( + const fapi2::Target&); + +/// @brief Cache Chiplet Reset +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_chiplet_reset( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_CHIPLET_RESET_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C new file mode 100644 index 0000000..0175c98 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -0,0 +1,282 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_setup.C +/// @brief Quad DPLL Setup +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// DPLL tune bits are not dependent on frequency +/// Put DPLL into bypass +/// Set DPLL syncmux sel +/// Set clock controller scan ratio to 1:1 as this is done at refclk speeds +/// Load the EX DPLL scan ring +/// Set clock controller scan ratio to 8:1 for future scans +/// Frequency is controlled by the Quad PPM +/// Actual frequency value for boot is stored into the Quad PPM by +/// p9_hcd_setup_evid.C in istep 2 +/// In real cache STOP exit, the frequency value is persistent +/// Enable the DPLL in the correct mode +/// non-dynamic +/// Slew rate established per DPLL team +/// Take the cache glitchless mux out of reset +/// (TODO: is there still a reset on P9?) +/// Remove DPLL bypass +/// Drop DPLL Tholds +/// Check for DPLL lock +/// Timeout: 200us +/// Switch cache glitchless mux to use the DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_dpll_setup.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//#define DPLL_LOCK_BIT, 50 +//#define DPLL_LOCK_MAX_POLL_LOOPS, 0x1600 +//#define DPLL_LOCK_DELAY_CYCLES, 0x10 +//#define STEP_SBE_DPLL_SETUP_LOCK, 1 +//#define STEP_SBE_DPLL_GMUX_SET, 2 +//#define STEP_SBE_DPLL_SETUP_COMPLETE, 3 + +// For a 2000GHz nest (500MHz Pervasive), 2ns clocks exists +// For a DPLL lock time of >150us from power on, 150000/2 = 75000 +// d75000 => 0x124F8 ----> round up to 0x15000 + +// For a 2400GHz nest (600MHz Pervasive), 1.667ns clocks exists +// For a DPLL lock time of >150us from power on, 150000/1.667 = 89982 +// d90000 => 0x15f90 ----> round up to 0x16000 + +//#define DPLL_LOCK_DELAY 0x10 +//#define DPLL_LOCK_LOOP_NUMBER 0x1600 + +//#define ex_dpll_lock_delay_mult 0x1600 +//#define ex_glsmux_post_delay_mult 0x1 + +//----------------------------------------------------------------------------- +// Procedure: Quad DPLL Setup +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_dpll_setup( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + FAPI_INF("EX Chiplet -> Start DPLL setup" ) + + // The setup of P0 happens external to this procedure + // P0 is set to point to either a single EX core, or to multiple EX + // cores using multicast + FAPI_DBG("EX Chiplet dpll_setup P0 -> 0x%02llx" , io_pore.p0.read()) + + // Skip DPLL and Glitchless mux setup for Sleep + // Glitchless mux change for the core (Sleep) done in + // p9_sbe_ex_chiplet_reset. + + // - ifsleep D0, glm_end + // >>> IPL/WINKLE + + // - dpll_start: + + // - setp1_mcreadand D0 + + FAPI_INF("Set up CPM PARM register for DPLL") + // = ld D0, EX_DPLL_CPM_PARM_REG_0x100F0152, P1 + FAPI_TRY(getScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + + // ----- Make sure that ff_bypass is set to "1" ----- + // This is necessary to ensure that the DPLL is in Mode 1. If not, + // the lock times will go from ~30us to 3-5ms + // Set bit 11 of DPLL Mode register 0x150F0152 + + FAPI_DBG("Put DPLL into Mode 1 by asserting ff_bypass.") + FAPI_DBG(">>> Work around <<<<: Also disabling ping-pong synchronizer" ) + // = ori D0, D0, (BIT(11)|BIT(32)) + data.setBit<11>().setBit<32>(); + + FAPI_DBG("Clear bits 15,16,18-23 and set bit 17 of DPLL reg 0x10F0152") + // = andi D0, D0, 0xFFFE00FFFFFFFFFF + // = ori D0, D0, BIT(17) + data.insertFromRight<15,9>(0x40); + + FAPI_DBG("Set slew rate to a modest value") + // = ori D0, D0, 0x8000000000000000 + // = std D0, EX_DPLL_CPM_PARM_REG_0x100F0152, P0 + data.setBit<0>(); + FAPI_TRY(putScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + + // ----- Clear dpllclk_muxsel (syncclk_muxsel) to "0" ----- + FAPI_INF("Reset syncclk_muxsel or dpllclk_muxsel") + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(1) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer().flush<1>().clearBit<1>())); + + // = sti EX_PMGP0_AND_0x100F0101, P0, ~(BIT(11)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().clearBit<11>())); + + // ----- Take DPLL out of bypass ----- + // Clear bit 5 of EX GP3 Register + FAPI_INF("EX Chiplet -> Take DPLL out of bypass" ) + // = sti EX_GP3_AND_0x100F0013, P0, ~(BIT(5)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer().flush<1>().clearBit<5>())); + + // ----- Drop DPLL tholds ----- + // Clear bit 3 of EX PMGP0 Register + FAPI_INF("EX Chiplet -> Drop internal DPLL THOLD" ) + // = sti EX_PMGP0_AND_0x100F0101, P0, ~(BIT(3)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().clearBit<3>())); + + // ----- Delay to wait for DPLL to lock ----- + // TODO: Determine whether or not we should POLL instead of put delay here. + // Wait for >150us + + FAPI_INF("Wait for DPLL to lock" ) + // - waits DPLL_LOCK_LOOP_NUMBER*DPLL_LOCK_DELAY + + // Check for lock + // - ldandi D0, EX_PMGP0_0x100F0100, P1, BIT(DPLL_LOCK_BIT) + // - braz D0, dpll_nolock + + // ----- Recycle DPLL in and out of bypass ----- + // Clear bit 5 of EX GP3 Register + FAPI_INF("EX Chiplet -> Recycle DPLL in and out of bypass" ) + // = sti EX_GP3_OR_0x100F0014, P0, BIT(5) + FAPI_TRY(putScom(i_target, EX_GP3_OR_0x100F0014, + fapi2:buffer().setBit<5>())); + + // = sti EX_GP3_AND_0x100F0013, P0, ~(BIT(5)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer().flush<1>().clearBit<5>())); + + FAPI_INF("EX Chiplet -> EX DPLL is locked" ) + // - updatestep STEP_SBE_DPLL_SETUP_LOCK, D0, P1 + + // - glm_start: + + // ----- Set Glitch-Less MUXes for IPL/Winkle case ---- + // For Sleep, the core glitchless mux is change earlier as the DPLL + // was already up and locked. + // + // Set various gl muxes to pass the output of the DPLLs to the clock grid. + + // Read-modify-write (vs sti AND and sti OR) is done so that glitchless + // mux change field change is atomic (eg 1 store) + // - setp1_mcreadand D1 + + // = ld D1,EX_PMGP0_0x100F0100,P1 + FAPI_TRY(getScom(i_target, EX_PMGP0_0x100F0100, data)); + + // IPL/Winkle - Switch glitchless mux primary source to 001 = DPLL for bits + // 27:29 + + // Note: GLM async reset occured in p9_sbe_ex_chiplet_reset. + + // Set tp_clkglm_sel_dc to "001" (EX PM GP0 bits 27-29) + FAPI_INF("EX Chiplet -> Set glitchless mux select for primary chiplet clock source to 001 ") + // Set tp_clkglm_eco_sel_dc to "0" (EX PM GP0 bit 30) + // Set the core glitchless mux to use the primary input (b00). + // EX PM GP0 bits 32-33) + FAPI_INF("EX Chiplet -> Set glitchless mux select for core and eco domain to 0 ") + // = andi D1, D1, ~(BIT(27)|BIT(28)|BIT(30)|BIT(32)|BIT(33)) + // = ori D1, D1, (BIT(29)) + data.insertFromRight<27,4>(0x2).inerstFromRight<32,2>(0x0); + + // Store the final result to the hardware + // = std D1,EX_PMGP0_0x100F0100,P0 + FAPI_TRY(putScom(i_target, EX_PMGP0_0x100F0100, data)); + + // - glm_end: + + // - updatestep STEP_SBE_DPLL_GMUX_SET, D0, P1 + + // ----- Drop ff_bypass to enable slewing ----- + // ----- (Change from Mode 1 to mode 2) ----- + // Clear bit 11 of DPLL Mode register 0x150F0152 + // CMO20131125-Further, drop the pp synchronizer bit32. + // CMO20131219-Keep the pp sync bit32 asserted to avoid x-leakage(HW276931). + FAPI_INF("EX Chiplet -> Clear ff_bypass to switch into slew-controlled mode") + // - setp1_mcreadand D1 + // = ld D1, EX_DPLL_CPM_PARM_REG_0x100F0152, P1 + // = andi D1, D1, ~(BIT(11)) + // = std D1, EX_DPLL_CPM_PARM_REG_0x100F0152, P0 + FAPI_TRY(getScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + data.clearBit<11>(); + FAPI_TRY(putScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + + // ----- Drop other tholds ----- + // Clear bit 3 of EX PM GP0 Register + // FAPI_INF("EX Chiplet -> Drop DPLL thold" ) + // sti EX_PMGP0_AND_0x100F0101,P0, ~(BIT(3)) + + // - updatestep STEP_SBE_DPLL_SETUP_COMPLETE, D0, P1 + FAPI_INF("EX Chiplet -> DPLL setup completed" ) + + // DEBUG only + // - setp1_mcreadand D1 + // = ld D0,EX_GP0_0x10000000,P1 + FAPI_TRY(getScom(i_target, EX_GP0_0x10000000, data)); + + // - dpll_nolock: + FAPI_ERR("EX_DPLL -> Failed to lock"); + // - reqhalt RC_SBE_DPLL_SETUP_NOLOCK + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H new file mode 100644 index 0000000..df13cf0 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_setup.H +/// @brief Quad DPLL Setup +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_DPLL_SETUP_H__ +#define __P9_HCD_CACHE_DPLL_SETUP_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_dpll_setup_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_dpll_setup_FP_t) ( + const fapi2::Target&); + +/// @brief Quad DPLL Setup +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_DPLL_REPAIR_RING - EQ target, uint32 +/// repair dpll ring content
+/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_dpll_setup( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_DPLL_SETUP_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C new file mode 100644 index 0000000..498ae79 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C @@ -0,0 +1,110 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.C +/// @brief Load GPTR and Time for EX non-core +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// to produce #G VPD contents +/// Check for the presence of core override GPTR ring from image +/// (this is new fvor P9) +/// if found, apply; if not, apply core GPTR from image +/// Check for the presence of core override TIME ring from image; +/// if found, apply; if not, apply core base TIME from image +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_gptr_time_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load GPTR and Time for EX non-core +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_gptr_time_initf( + const fapi2::Target& i_target) +{ + +#if 0 + + // Set EX scan ratio to 1:1 as EX is still at refclock + FAPI_INF(" : Set EX scan ratio to 1:1 ..."); + // = sti EX_OPCG_CNTL0_0x10030002, P0, 0x0 + FAPI_TRY(fapi2::putScom(i_target, EX_OPCG_CNTL0_0x10030002, 0x0)); + + // scan ring content shared among all chiplets + FAPI_DBG("Scanning EX GPTR rings...") + // - load_ring ex_gptr_perv skipoverride=1 + // - load_ring ex_gptr_dpll skipoverride=1 + // - load_ring ex_gptr_l3 skipoverride=1 + // - load_ring ex_gptr_l3refr skipoverride=1 + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX TIME rings...") + // - load_ring_vec_ex ex_time_eco + + + // Set EX scan ratio back to 8:1 + FAPI_INF(" : Set EX scan ratio to 8:1 ..."); + // Inputs: A1 and P0 and D0, destroys D0 & D1 + // - .pibmem_port (PORE_SPACE_PIBMEM & 0xf) + // - lpcs P1, PIBMEM0_0x00080000 + // - ld D0, ex_scan_ratio_override, P1 + // - bsr set_scan_ratio_d0 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H new file mode 100644 index 0000000..17d001f --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.H +/// @brief Load GPTR and Time for EX non-core +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_GPTR_TIME_INIT_H__ +#define __P9_HCD_CACHE_GPTR_TIME_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_gptr_time_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_gptr_time_initf_FP_t) ( + const fapi2::Target&); + +/// @brief Load GPTR and Time for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_GPTR_TIME_RING - EX target, uint32 +/// pointer to RS4 content.
+/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_gptr_time_initf( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_GPTR_TIME_INIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_initf.C b/src/ppe/hwp/cache/p9_hcd_cache_initf.C new file mode 100644 index 0000000..630940b --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_initf.C @@ -0,0 +1,99 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.C +/// @brief EX (non-core) scan init +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// Check for the presence of cache FUNC override rings from image; +/// if found, apply; if not, apply cache base FUNC rings from image +/// Note: FASTINIT ring (eg CMSK ring) is setup at this point to limit the +/// stumps that participate in FUNC ring scanning (this is new for P9). +/// (TODO to make sure the image build support is in place) +/// Note: all caches that are in the Cache Multicast group will be +/// initialized to the same values via multicast scans +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: EX (non-core) scan init +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_initf( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + // - load_ring ex_lbst_eco conditional_override=1 + // - load_ring ex_abfa_eco conditional_override=1 + // - load_ring ex_cmsk_eco conditional_override=1 + // - load_ring ex_func_perv conditional_override=1 + // - load_ring ex_func_l3 conditional_override=1 + // - load_ring ex_func_l3refr conditional_override=1 + + //Sim Speedup for L3 refresh cycles + // - load_ring ex_regf_l3 conditional_override=1 + // - load_ring ex_regf_l3refr conditional_override=1 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_initf.H b/src/ppe/hwp/cache/p9_hcd_cache_initf.H new file mode 100644 index 0000000..9f7ffdc --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.H +/// @brief EX (non-core) scan init +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_INITF_H__ +#define __P9_HCD_CACHE_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) ( + const fapi2::Target&); + +/// @brief EX (non-core) scan init +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_L2_FUNC_RING - EX target, uint32 +/// @attritem ATTR_CACHE_L3_FUNC_RING - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_initf( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_INITF_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C new file mode 100644 index 0000000..8e1c82e --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.C +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from OCC code that are put somewhere TBD +/// (TODO . revisit with OCC FW team) +/// OCC FW sets up value in the TBD SCOM section +/// This was not leverage in P8 with the demise of CPMs +/// Placeholder at this point +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_occ_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX OCC runtime SCOMS +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_occ_runtime_scom( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, occ_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + FAPI_INF("Launching OCC Runtime SCOM routine") + // - bsrd D0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H new file mode 100644 index 0000000..e82b6b2 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.H +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_occ_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_occ_runtime_scom_FP_t) ( + const fapi2::Target&); + + +/// @brief EX OCC runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_OCC_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_occ_runtime_scom( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_poweron.C b/src/ppe/hwp/cache/p9_hcd_cache_poweron.C new file mode 100644 index 0000000..0aa81a1 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_poweron.C @@ -0,0 +1,84 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_poweron.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_poweron.C +/// @brief Cache Chiplet Power-on +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Command the cache PFET controller to power-on +/// Check for valid power on completion +/// Polled Timeout: 100us +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_poweron.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Cache Chiplet Power-on +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_poweron( + const fapi2::Target& i_target, + const uint32_t i_operation) +{ + +#if 0 + fapi2::buffer data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_poweron.H b/src/ppe/hwp/cache/p9_hcd_cache_poweron.H new file mode 100644 index 0000000..89bcffc --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_poweron.H @@ -0,0 +1,66 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_poweron.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_poweron.H +/// @brief Cache Chiplet Power-on +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_POWERON_H__ +#define __P9_HCD_CACHE_POWERON_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_poweron_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_poweron_FP_t) ( + const fapi2::Target&, + const uint32_t); + + +/// @brief Cache Chiplet Power-on +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_* +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_poweron( + const fapi2::Target& i_target, + const uint32_t i_operation); + + +} // extern C + +#endif // __P9_HCD_CACHE_POWERON_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C new file mode 100644 index 0000000..88a0518 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C @@ -0,0 +1,171 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.C +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates by FSP/Host(including HostServices and Hypervisors) +/// that are put on the cache image by STOP API calls +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (the SBE case), return +/// Else call the function at the pointer; pointer is filled in by +/// STOP image build +/// Powerbus (MCD) and L3 BAR settings +/// Runtime FIR mask updates from PRD +/// L2/L3 Repairs +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_ras_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX FSP/HOST runtime scoms +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_ras_runtime_scom( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, sp_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching SP Runtime SCOM routine") + // - bsrd D0 + // - 1: + // + + // Run the SCOM sequence if the SCOM procedure is defined. + // - la A0, host_runtime_scom + // - ld D1, 0, A0 + // - braz D1, 1f + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Disable the AISS to allow the override + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~(BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = ori D0, D0, (BIT(15)) + // = andi D0, D0, ~(BIT(21)) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + + // Branch to sub_slw_runtime_scom() + FAPI_INF("Launching Host Runtime SCOM routine") + // - bsrd D1 + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + + // - bra 2f + // - 1: + + // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - 2: + + // If using cv_multicast, we need to set the magic istep number here + // - la A0, p9_sbe_select_ex_control + // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX + // - braz D0, 3f + FAPI_DBG("Setting istep num to magic number because cv_multicast is set") + // - lpcs P1, MBOX_SBEVITAL_0x0005001C + // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) + // - 3: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H new file mode 100644 index 0000000..ec9a389 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.H +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_ras_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_ras_runtime_scom_FP_t) ( + const fapi2::Target&); + +/// @brief EX FSP/Host runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_RAS_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_ras_runtime_scom( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C new file mode 100644 index 0000000..e986a81 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C @@ -0,0 +1,87 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.C +/// @brief Load Repair ring for EX non-core +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: Repair Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in /// MVPD, but SBE image is customized with rings for booting cores +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_repair_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load Repair ring for cache +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_repair_initf( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX REPAIR rings...") + // - load_ring_vec_ex ex_repr_eco + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H new file mode 100644 index 0000000..ab8484f --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.H +/// @brief Load Repair ring for EX non-core +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_REPAIR_INITF_H__ +#define __P9_HCD_CACHE_REPAIR_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_repair_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_repair_initf_FP_t) ( + const fapi2::Target&); + + +/// @brief Load Repair ring for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_REPAIR_RING - EX target, uint32 +/// pointer to RS4 content, VPD #R Keyword content(RS4)
+/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_repair_initf( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_REPAIR_INITF_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_runinit.C b/src/ppe/hwp/cache/p9_hcd_cache_runinit.C new file mode 100644 index 0000000..eb6f5fe --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_runinit.C @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_runinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_runinit.C +/// @brief execute all cache init procedures +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_runinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_runinit( + const fapi2::Target& i_target) +{ + return fapi2::FAPI2_RC_SUCCESS; + +#if 0 + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; +#endif + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_runinit.H b/src/ppe/hwp/cache/p9_hcd_cache_runinit.H new file mode 100644 index 0000000..2b22d35 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_runinit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_runinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_runinit.H +/// @brief execute all cache init procedures +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_RUNINIT_H__ +#define __P9_HCD_CACHE_RUNINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_runinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_runinit_FP_t) ( + const fapi2::Target&); + + +/// @brief execute all cache init procedures +/// +/// @param [in] i_target TARGET_TYPE_PROC_CHIP target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_runinit( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_RUNINIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scomcust.C b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.C new file mode 100644 index 0000000..789f954 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scomcust.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.C +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// If CME, request PCB Mux. +/// Poll for PCB Mux grant +/// Else (SBE) +/// Nop (as the CME is not running in bringing up the first Core) +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_scomcust.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: Core Chiplet PCB Arbitration +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_scomcust( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + //Dynamically built (and installed) routine that is inserted by the .XIP + //Customization. process. (New for P9) + //(TODO: this part of the process is a placeholder at this point) + //Dynamically built pointer where a NULL is checked before execution + //If NULL (a potential early value); return + //Else call the function at the pointer; + //pointer is filled in by XIP Customization + //Customization items: + //Epsilon settings scan flush to super safe + //Customize Epsilon settings for system config + //LCO setup (chiplet specific) + //FW setups up based victim caches + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scomcust.H b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.H new file mode 100644 index 0000000..9837513 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scomcust.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.H +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_SCOMCUST_H__ +#define __P9_HCD_CACHE_SCOMCUST_H__ +extern "C" +{ + +/// @typedef p9_hcd_cache_scomcust_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_scomcust_FP_t) ( + const fapi2::Target&); + + +/// @brief Core Chiplet PCB Arbitration +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_scomcust( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_SCOMCUST_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scominit.C b/src/ppe/hwp/cache/p9_hcd_cache_scominit.C new file mode 100644 index 0000000..869de65 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scominit.C @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scominit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.C +/// @brief Cache Customization SCOMs +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Apply any SCOM initialization to the cache +/// Stop L3 configuration mode +/// Configure Trace Stop on Xstop +/// DTS Initialization sequense +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_scominit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Cache Customization SCOMs +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_scominit( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + /////// + // NCU + /////// + + /////// + // L3 + /////// + + FAPI_DBG("Configuring L3 disable"); + // - l3_setup L3_SETUP_ACTION_DISABLE, L3_SETUP_UNIT_L3 + + /////// + // OHA + /////// + + FAPI_DBG("Enable OHA to accept idle operations \ + by removing idle state override"); + // - setp1_mcreadand D1 + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + + //FAPI_DBG("Read OHA_MODE value: 0x%16llx", io_pore.d0.read()); + // = andi D0, D0, ~BIT(6) + data.clearBit<6>(); + + //FAPI_DBG("Updated OHA_MODE value: 0x%16llx", io_pore.d0.read()); + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + + // set trace stop on checkstop + // Get the ECID to apply trace setup to only Murano DD2+ / Venice + // - lpcs P1, STBY_CHIPLET_0x00000000 + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, (CFAM_CHIP_ID_CHIP_MASK | CFAM_CHIP_ID_MAJOR_EC_MASK) + // - cmpibraeq D0, 1f, (CFAM_CHIP_ID_MURANO | CFAM_CHIP_ID_MAJOR_EC_1 ) + + FAPI_DBG("Configuring EX chiplet trace arrays \ + to stop on checkstop/recoverable errors") + // = sti GENERIC_DBG_MODE_REG_0x000107C0, P0, BIT(7) | BIT(8) + FAPI_TRY(putScom(i_target, GENERIC_DBG_MODE_REG_0x000107C0, + fapi2:buffer().insertFromRight<7,2>(0x3))); + + // = sti GENERIC_DBG_TRACE_REG2_0x000107CB, P0, BIT(17) + FAPI_TRY(putScom(i_target, GENERIC_DBG_TRACE_REG2_0x000107CB, + fapi2:buffer().setBit<17>())); + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scominit.H b/src/ppe/hwp/cache/p9_hcd_cache_scominit.H new file mode 100644 index 0000000..0fd37c6 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scominit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scominit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.H +/// @brief Cache Customization SCOMs +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_SCOMINIT_H__ +#define __P9_HCD_CACHE_SCOMINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_scominit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_scominit_FP_t) ( + const fapi2::Target&); + + +/// @brief Cache Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_scominit( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_SCOMINIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_startclocks.C b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.C new file mode 100644 index 0000000..3731f2e --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.C @@ -0,0 +1,275 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_startclocks.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.C +/// @brief Quad Clock Start +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Set (to be sure they are set under all conditions) core logical fences +/// (new for P9) +/// Drop pervasive thold +/// Setup L3 EDRAM/LCO +/// Drop pervasive fence +/// Reset abst clock muxsel, sync muxsel +/// Set fabric node/chip ID from the nest version +/// Clear clock controller scan register before start +/// Start arrays + nsl regions +/// Start sl + refresh clock regions +/// Check for clocks started +/// If not, error +/// Clear force align +/// Clear flush mode +/// Drop the chiplet fence to allow PowerBus traffic +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_cache_startclocks.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +#define STEP_EX_START_CLOCKS_NSL 0x1 +#define STEP_EX_START_CLOCKS_SL 0x2 +#define STEP_EX_START_CLOCKS_RUNNING 0x3 +#define STEP_EX_START_CLOCKS_SUCCESS 0x4 + + +//------------------------------------------------------------------------------ +// Procedure: Quad Clock Start +//------------------------------------------------------------------------------ + + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_startclocks( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + FAPI_INF(": \ + P8 Start EX-Clocks started"); + + // Drop the Pervasive THOLD + // PM Exit States: WINKLE_EXIT_DROP_PERV_THOLD + // = sti EX_PMGP0_AND_0x100F0101,P0, ~(BIT(4)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().clearBit<4>())); + + FAPI_DBG("Enabling L3 EDRAM/LCO setup"); + // - l3_setup L3_SETUP_ACTION_ENABLE, L3_SETUP_UNIT_L3_EDRAM + + // Drop perv fence GP0.63 multicast scomreg write + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(63) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer().flush<1>().clearBit<63>())); + + // Reset abstclk_muxsel, synclk_muxsel (io_clk_sel) + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BITS(0,2) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer().flush<1>().insertFromRight<0,2>(0x0))); + + // Set ABIST_MODE_DC for core chiplets (core recovery) + // = sti GENERIC_GP0_OR_0x00000005, P0, BIT(11)|BIT(13) + FAPI_TRY(putScom(i_target, GENERIC_GP0_OR_0x00000005, + fapi2:buffer().setBit<11>().setBit<13>())); + + // set fabric node/chip ID values (read from nest chiplet) + // read from nest chiplet + // - lpcs P1, NEST_CHIPLET_0x02000000 + // - ldandi D0, NEST_GP0_0x02000000, P1, BITS(40, 6) + // = std D0, GENERIC_GP0_OR_0x00000005, P0 + //FAPI_TRY(putScom(i_target, GENERIC_GP0_OR_0x00000005, data)); + + // Write ClockControl, Scan Region Register, + // set all bits to zero prior clock start + // = sti GENERIC_CLK_SCANSEL_0x00030007, P0, 0x0000000000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_SCANSEL_0x00030007, 0x0)); + + // Write ClockControl, Clock Region Register, Clock Start command + // (arrays + nsl only, not refresh clock region) EX Chiplet + // = sti GENERIC_CLK_REGION_0x00030006, P0, 0x4FF0060000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_REGION_0x00030006, + fapi2:buffer(0x4FF0060000000000))); + // - updatestep STEP_EX_START_CLOCKS_NSL, D0, P1 + + // Write ClockControl, Clock Region Register, Clock Start command + // (sl + refresh clock region) EX Chiplet + // = sti GENERIC_CLK_REGION_0x00030006, P0, 0x4FF00E0000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_REGION_0x00030006, + fapi2:buffer(0x4FF00E0000000000))); + // - updatestep STEP_EX_START_CLOCKS_SL, D0, P1 + + // Read Clock Status Register (EX chiplet) + // check for bits 27:29 eq. zero, no tholds on + // 27 ROX CLOCK_STATUS_DPLL_FUNC_SL status of dpll_func_sl_thold + // 28 ROX CLOCK_STATUS_DPLL_FUNC_NSL status of dpll_func_nsl_thold + // output not used + // 29 ROX CLOCK_STATUS_DPLL_ARY_NSL status of dpll_ary_nsl_thold + // output not used + + // Needed to resolve SLW reading using a multicast group + // Get P1 setup for the chiplets to be targeted. + // - setp1_mcreadand D0 + + // = ld D0, GENERIC_CLK_STATUS_0x00030008, P1 + FAPI_TRY(getScom(i_target, GENERIC_CLK_STATUS_0x00030008, data)); + // - xori D0, D0, 0x00000003FFFFFFFF + // - branz D0, error_clock_start + + FAPI_DBG(": \ + EX clock running now"); + // - updatestep STEP_EX_START_CLOCKS_RUNNING, D0, P1 + + // Read the Global Checkstop FIR of dedicated EX chiplet + // - setp1_mcreador D0 + // = ld D0, GENERIC_XSTOP_0x00040000, P1 + FAPI_TRY(getScom(i_target, GENERIC_XSTOP_0x00040000, data)); + // - branz D0, error_checkstop_fir + + FAPI_DBG(": \ + All checkstop FIRs on initialized EX are zero"); + + // Clear force_align in all Chiplet GP0 + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(3) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer().flush<1>().clearBit<3>())); + + // Clear flushmode_inhibit in Chiplet GP0 + // Can't do this on Murano & Venice DD1.x due to a logic bug in L3 HW250462 + // - lpcs P1, PCBMS_DEVICE_ID_0x000F000F + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, CFAM_CHIP_ID_MAJOR_EC_MASK + // - cmpibraeq D0, 1f, CFAM_CHIP_ID_MAJOR_EC_1 + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(2) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer().flush<1>().clearBit<2>())); + // - 1: + + // Clear core2cache and cache2core fences. Necessary for Sleep, + // redundant (already clear) but not harmful for IPL/Winkle + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(20)|BIT(21)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().insertFromRight<20,2>(0x0))); + + // Disable PM and DPLL override + FAPI_INF(": \ + Disable PM and DPLL override"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(0)|BIT(3)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().insertFromRight<0,4>(0x6))); + + // PM Exit States: WINKLE_EXIT_WAIT_ON_OHA + // Drop fence GP3.18 to unfence the chiplet + // CMO-20130516: First clear the pbus purge request bit(14) from AISS + // - setp1_mcreador D0 + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + data.clearBit<1>(); + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~BIT(14) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + FAPI_TRY(getScom(i_target, EX_OHA_AISS_IO_REG_0x10020014, data)); + data.clearBit<14>(); + FAPI_TRY(putScom(i_target, EX_OHA_AISS_IO_REG_0x10020014, data)); + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + data.setBit<1>(); + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + // Now drop pb fence bit(18) + // = sti GENERIC_GP3_AND_0x000F0013,P0, ~BIT(18) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer().flush<1>().clearBit<18>())); + + // Drop fence GP3.26 to allow PCB operations to the chiplet + // = sti GENERIC_GP3_AND_0x000F0013,P0, ~BIT(26) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer().flush<1>().clearBit<26>())); + // - updatestep STEP_EX_START_CLOCKS_SUCCESS, D0, P1 + FAPI_INF(": \ + Exiting procedure successfully"); + + // - ifidle D0, 1f + //Not idle Check secure mode + // - ifbitclrscom D1, D1, OTPC_M_SECURITY_SWITCH_0x00010005, P1, 1, 1f + //Trusted boot is set, set core trusted boot. + // = sti EX_TRUSTED_BOOT_EN_0x10013C03, P0, BIT(0) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer().flush<1>().clearBit<0>())); + // - 1: + +//------------------------------------------------------------------------------ +// ERROR -- Clocks failed to start +//------------------------------------------------------------------------------ +error_clock_start: + FAPI_ERR(": \ + Clock Start Error on EX detected"); + // - reqhalt RC_SBE_EX_STARTCLOCKS_CLOCKS_NOT_STARTED + +//------------------------------------------------------------------------------ +// ERROR -- Checkstop detected +//------------------------------------------------------------------------------ +error_checkstop_fir: + FAPI_ERR(": \ + Checkstop FIR on initialized EX is not zero, \ + VITAL register was updated"); + // - reqhalt RC_SBE_EX_STARTCLOCKS_CHIP_XSTOPPED + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_startclocks.H b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.H new file mode 100644 index 0000000..a6aa1d6 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_startclocks.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.H +/// @brief Quad Clock Start +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Sangeetha T S +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CACHE_STARTCLOCKS_H__ +#define __P9_HCD_CACHE_STARTCLOCKS_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_startclocks_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_startclocks_FP_t) ( + const fapi2::Target&); + +/// @brief Quad Clock Start +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_startclocks( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_STARTCLOCKS_H__ diff --git a/src/ppe/hwp/core/Makefile b/src/ppe/hwp/core/Makefile new file mode 100644 index 0000000..9842d1f --- /dev/null +++ b/src/ppe/hwp/core/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/core/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the core hardware procedure code. See the +# "corehcdfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/cache +export SUB_OBJDIR = /core + +include img_defs.mk +include corehcdfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(CACHE_OBJECTS)) + +libcore.a: core + $(AR) crs $(OBJDIR)/libcore.a $(OBJDIR)/*.o + +.PHONY: clean core +core: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ppe/hwp/core/corehcdfiles.mk b/src/ppe/hwp/core/corehcdfiles.mk new file mode 100644 index 0000000..364de0c --- /dev/null +++ b/src/ppe/hwp/core/corehcdfiles.mk @@ -0,0 +1,65 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/core/corehcdfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file corehcdfiles.mk +# +# @brief mk for including core hcode object files +# +# @page ChangeLogs Change Logs +# @section corehcdfiles.mk +# @verbatim +# +# +# Change Log ****************************************************************** +# Flag Defect/Feature User Date Description +# ------ -------------- ---------- ------------ ----------- +# +# @endverbatim +# +########################################################################## +# Object Files +########################################################################## + +CACHE-CPP-SOURCES += p9_hcd_core_arrayinit.C +CACHE-CPP-SOURCES += p9_hcd_core_chiplet_init.C +CACHE-CPP-SOURCES += p9_hcd_core_chiplet_reset.C +CACHE-CPP-SOURCES += p9_hcd_core_gptr_time_initf.C +CACHE-CPP-SOURCES += p9_hcd_core_initf.C +CACHE-CPP-SOURCES += p9_hcd_core_occ_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_core_pcb_arb.C +CACHE-CPP-SOURCES += p9_hcd_core_poweron.C +CACHE-CPP-SOURCES += p9_hcd_core_ras_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_core_repair_initf.C +CACHE-CPP-SOURCES += p9_hcd_core_runinit.C +CACHE-CPP-SOURCES += p9_hcd_core_scomcust.C +CACHE-CPP-SOURCES += p9_hcd_core_scominit.C +CACHE-CPP-SOURCES += p9_hcd_core_startclocks.C + +CACHE-C-SOURCES += +CACHE-S-SOURCES += + +CACHE_OBJECTS += $(CACHE-CPP-SOURCES:.C=.o) +CACHE_OBJECTS += $(CACHE-C-SOURCES:.c=.o) +CACHE_OBJECTS += $(CACHE-S-SOURCES:.S=.o) + diff --git a/src/ppe/hwp/core/p9_hcd_core.H b/src/ppe/hwp/core/p9_hcd_core.H new file mode 100644 index 0000000..a96280f --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core.H @@ -0,0 +1,54 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core.H +/// @brief Core Chiplet Procedure Includes +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_H__ +#define __P9_HCD_CORE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // __P9_HCD_CORE_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_arrayinit.C b/src/ppe/hwp/core/p9_hcd_core_arrayinit.C new file mode 100644 index 0000000..58c6ecc --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_arrayinit.C @@ -0,0 +1,156 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_arrayinit.C +/// @brief Core Initialize arrays +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Use ABIST engine to zero out all arrays +/// Upon completion, scan0 flush all rings except Vital,Repair,GPTR,and TIME +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_arrayinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Core Initialize arrays +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_arrayinit( + const fapi2::Target& i_target) + +{ + +#if 0 + fapi2::buffer data; + + // Procedure Prereq : P0 is pointing to the targeted EX chiplet + // submodules: + // seeprom_array_init_module + // ex_scan0 + + FAPI_INF(" : \ + *** Array Init and Scan0 Cleanup for EX Chiplets ***"); + + // SBE Address Base Register Setups + // Setup PRV_BASE_ADDR1; points to selected EX chiplet + // - mr P1, P0 + FAPI_INF(" : \ + Copy selected EX info from P0 to P1"); + + // Step 1: Array Init for selected EX chiplet + // ARRAY INIT module -> see p9_sbe_tp_array_init.S + // + // At entry: + // + // P1 : The chiplet ID/Multicast Group + // D1 : Clock Regions for Array Init + // + // At exit: + // + // P0, D0, D1, CTR : destroyed + // P1, A0, A1 : maintained + // + FAPI_INF(" : \ + Calling Array Init Subroutine"); + + // >>> Sleep + // - li D1, SCAN_CLK_CORE_ONLY + + // Execute the array init + // - bsr seeprom_array_init_module + + // Restore P0 with selected EX chiplet info + // - mr P0, P1 + FAPI_INF(" : \ + Copy selected EX info back from P1 to P0"); + + // Step 2: Scan0 for selected EX chiplet except PRV, GPTR, TIME and DPLL + FAPI_INF(" : \ + Calling Scan0 Subroutine"); + + // taken from p9_sbe_ex_chiplet_init + + // >>> Sleep scan flush - core only + + // Hook to bypass in Sim + // - hooki 0, 0xFF04 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,2f + + FAPI_DBG("EX ArrayInit: Scan0 Module executed: \ + Scan all core chains except GPTR and TIME"); + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + + // - .rept P9_SCAN0_FUNC_REPEAT + // - ex_scan0 SCAN_CORE_ALL_BUT_GPTRTIMEREP, SCAN_CLK_CORE_ONLY + // - .endr + // - 2: + + FAPI_INF(" : \ + *** End of Procedure ***"); + + return fapi2::FAPI2_RC_SUCCESS; + +clean_up: + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_arrayinit.H b/src/ppe/hwp/core/p9_hcd_core_arrayinit.H new file mode 100644 index 0000000..b0eeb5e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_arrayinit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_arrayinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_arrayinit.H +/// @brief Core Initialize arrays +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_ARRAYINIT_H__ +#define __P9_HCD_CORE_ARRAYINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_arrayinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_arrayinit_FP_t) ( + const fapi2::Target&); + +/// @brief Core Initialize arrays +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_arrayinit( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_ARRAYINIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_init.C b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.C new file mode 100644 index 0000000..3d3763a --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.C @@ -0,0 +1,136 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_init.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_init.C +/// @brief Core Flush/Initialize +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Switch the core glitchless mux to allow DPLL clocks on the clock grid +/// Scan0 flush all chiplet rings except VITAL, GPTR and TIME +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_chiplet_init.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +//#define SIM_PLL +//#define SIM_SPEEDUP +////#define SCAN0_DISABLE +//#define STEP_CHIPLET_INIT_0 0x0 // Resetting DPLL +//#define STEP_CHIPLET_INIT_1 0x1 // Core+ECO glmux switch (IPL/Winkle) +//#define STEP_CHIPLET_INIT_2 0x2 // Core glmux switch (Sleep) +//#define STEP_CHIPLET_INIT_3 0x3 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_4 0x4 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_5 0x5 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_6 0x6 // Before Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_7 0x7 // After Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_8 0x8 // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_9 0x9 // After Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_A 0xA // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_B 0xB // After Core Func flush for Sleep +//#define PORE_REFCLK_CYCLES 1 // \todo need real value for hdw +//#define DPLL_LOCK_DELAY 8192*PORE_REFCLK_CYCLES + +//------------------------------------------------------------------------------ +// Procedure: Core Flush/Initialize +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_chiplet_init( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + // Procedure Prereq: + // p9_sbe_ex_chiplet_reset, p9_sbe_ex_dpll_initf, p9_sbe_ex_pll_initf + + FAPI_INF(": Entering procedure"); + + // Look for PSCOM error on any chip, fail if we find one + // scan0 flush all configured chiplet rings except EX DPLL + // call ex_scan0_module( ) + + // >>> Sleep GPTR flush - core only + // This is done after the swing of the Glitchless Mux above + // Hook to bypass in sim while providing a trace + + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF04 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Reset: Scan0 Module executed for Sleep: \ + Scan the all but GPTR/TIME/REP rings"); + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + // - updatestep STEP_CHIPLET_INIT_A, D0, P1 + // - .rept P9_SCAN0_FUNC_REPEAT + // - ex_scan0 SCAN_CORE_ALL_BUT_GPTRTIMEREP, SCAN_CLK_CORE_ONLY + // - .endr + // - updatestep STEP_CHIPLET_INIT_B, D0, P1 + // - 1: + + FAPI_INF(": Exiting procedure"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_init.H b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.H new file mode 100644 index 0000000..be081ef --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_init.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_init.H +/// @brief Core Flush/Initialize +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_CHIPLET_INIT_H__ +#define __P9_HCD_CORE_CHIPLET_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_chiplet_init_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_init_FP_t) ( + const fapi2::Target&); + + +/// @brief Core Flush/Initialize +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_chiplet_init( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_CHIPLET_INIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C new file mode 100644 index 0000000..1874f0f --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C @@ -0,0 +1,196 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_reset.C +/// @brief Core Chiplet Reset +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Reset chiplet logic +/// (TODO: check with Andreas on the effect of a CME based Endpoint reset +/// relative to the CorePPM path) +/// Scan0 flush entire core chiplet +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_chiplet_reset.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +// GP3 Bits +// 1 - PCB_EP_RESET +// 2 - GLMMUX Reset +// 3 - PLL_TEST Enable +// 4 - PLLRST - PLL Reset +// 5 - PLL Bypass +// 11 - D_MODE for Vital +// 13 - MPW2 for Vital +// 14 - PMW1 for Vital +// 18 - FENCE_EN for chiplet +// 22 - Resonant Clock disable +// 23:24 - Glitchless Mux Sel +// 25: - ?? (set because System Pervasive flow does this) +// Background: system pervasive as the following setting in their tests: +// 7C1623C000000000 +// Bits set: +// 1, 2, 3, 4, 5, 11, 13, 14, 18, 22, 23, 24, 25 +//#define GP3_INIT_VECTOR (BITS(1,5)|BIT(11)|BIT(13)|BIT(14)|BIT(18)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) + +// hang counter inits +//#define HANG_P1_INIT 0x0400000000000000 +//#define PCB_SL_ERROR_REG_RESET 0xFFFFFFFFFFFFFFFF +//#define STEP_CHIPLET_RESET_1 0x1 // After start of vital clocks +//#define STEP_CHIPLET_RESET_2 0x2 // After fence drop +//#define STEP_CHIPLET_RESET_3 0x3 // Before GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_4 0x4 // After GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_5 0x5 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_6 0x6 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_7 0x7 // Before GPTR flush for Sleep +//#define STEP_CHIPLET_RESET_8 0x8 // After GPTR flush for Sleep + +//------------------------------------------------------------------------------ +// Procedure: Core Chiplet Reset +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_chiplet_reset( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + ///////////////////////////////////////////////////////////////// + // repeat some init steps of chiplet_init + ///////////////////////////////////////////////////////////////// + + // If there is a unused, powered-off EX chiplet which needs to be + // configured in the following steps to setup the PCB endpoint. + + // Skip the PCB endpoint config steps for sleep so that fences don't + // get dropped (eg by dropping chiplet_enable (GP3(0)). + + // The following is performed for both IPL/Winkle and Sleep + + // Note: These are executed for sleep as well as these fences will have + // already been dropped + + FAPI_DBG(": \ + Remove pervasive ECO fence;"); + // ECO Fence in 22 + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(22)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().clearBit<22>())); + + FAPI_DBG(": \ + Remove winkle mode before scan0 on EX chiplets is executed"); + // PM Exit States: WINKLE_EXIT_DROP_ELEC_FENCE + + FAPI_DBG(": \ + Remove logical pervasive/pcbs-pm fence"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(39)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer().flush<1>().clearBit<39>())); + + FAPI_DBG(": \ + Remove PB Winkle Electrical Fence GP3(27)"); + // = sti EX_GP3_AND_0x100F0013,P0,~(BIT(27)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer().flush<1>().clearBit<27>())); + + FAPI_DBG(": \ + Configuring chiplet hang counters") ; + // = sti EX_HANG_P1_0x100F0021,P0,HANG_P1_INIT + FAPI_TRY(putScom(i_target, EX_HANG_P1_0x100F0021, HANG_P1_INIT)); + // - updatestep STEP_CHIPLET_RESET_2, D0, P1 + + ////////////////////////////////////////////////////////////// + // perform scan0 module for pervasive chiplet (GPTR_TIME_REPR) + ////////////////////////////////////////////////////////////// + + // For the Sleep case, the DPLL is running but the core mesh is force to + // the "constant" or "off" state. In order to flush or scan, the mesh must + // be reenabled via the Glitchless Mux. + + // Read-modify-write (vs sti AND and sti OR) is done so that glitchless + // mux change field change is atomic (eg 1 store) + // - setp1_mcreadand D1 + // = ld D1,EX_PMGP0_0x100F0100,P1 + FAPI_TRY(fapi2::getScom(i_target, EX_PMGP0_0x100F0100, data)); + + // Set the core glitchless mux to use the primary input (b00). + // Upon Sleep entry, hardware will switch the glitchless mux to 0b10 + // (constant). EX PM GP0 bits 32-33) + FAPI_INF("EX Chiplet -> Set glitchless mux select for core domain to 00 ") + // = andi D1, D1, ~(BIT(32)|BIT(33)) + + // Store the final result to the hardware + // = std D1,EX_PMGP0_0x100F0100,P0 + data.insertFromRight<32,2>(0x0); + FAPI_TRY(putScom(i_target, EX_PMGP0_0x100F0100, data)); + // - updatestep STEP_CHIPLET_RESET_7, D0, P1 + + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF03 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Reset: Scan0 Module executed for Sleep: \ + Scan the GPTR/TIME/REP rings"); + + // - .rept P9_SCAN0_GPTR_REPEAT + // - ex_scan0 SCAN_CORE_GPTR_TIME_REP, SCAN_CLK_CORE_ONLY + // - .endr + // - 1: + // - updatestep STEP_CHIPLET_RESET_8, D0, P1 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H new file mode 100644 index 0000000..6d95c93 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_reset.H +/// @brief Core Chiplet Reset +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_CHIPLET_RESET_H__ +#define __P9_HCD_CORE_CHIPLET_RESET_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_chiplet_reset_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_reset_FP_t) ( + const fapi2::Target&); + + +/// @brief Core Chiplet Reset +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_chiplet_reset( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_CHIPLET_RESET_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C new file mode 100644 index 0000000..e6b54ed --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C @@ -0,0 +1,112 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_gptr_time_initf.C +/// @brief Load Core GPTR and Time rings +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// to produce #G VPD contents +/// Check for the presence of core override GPTR ring from image +/// (this is new for P9) +/// if found, apply; if not, apply core GPTR from image +/// Check for the presence of core override TIME ring from image; +/// if found, apply; if not, apply core base TIME from image +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_gptr_time_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Load Core GPTR and Time rings +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_gptr_time_initf( + const fapi2::Target& i_target) +{ + +#if 0 + + // >>> For sleep, bypass the pull back of the scan ratio + // - ifsleep D0, 1f + // Set EX scan ratio to 1:1 as EX is still at refclock + FAPI_INF(" : \ + Set EX scan ratio to 1:1 ...") + // = sti EX_OPCG_CNTL0_0x10030002, P0, 0x0 + FAPI_TRY(fapi2::putScom(i_target, EX_OPCG_CNTL0_0x10030002, 0x0)); + // - 1: + + // scan ring content shared among all chiplets + FAPI_DBG("Scanning EX core GPTR rings...") + // - load_ring ex_gptr_core skipoverride=1 + // - load_ring ex_gptr_l2 skipoverride=1 + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX core TIME rings...") + // - load_ring_vec_ex ex_time_core + + // Set EX scan ratio back to 8:1 + FAPI_INF(" : \ + Set EX scan ratio to 8:1 ...") + //Inputs: A1 and P0 and D0, destroys D0 & D1 + // - .pibmem_port (PORE_SPACE_PIBMEM & 0xf) + // - lpcs P1, PIBMEM0_0x00080000 + // - ld D0, ex_scan_ratio_override, P1 + // - bsr set_scan_ratio_d0 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H new file mode 100644 index 0000000..881f493 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_gptr_time_initf.H +/// @brief Load Core GPTR and Time rings +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_GPTR_TIME_INIT_H__ +#define __P9_HCD_CORE_GPTR_TIME_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_gptr_time_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_gptr_time_initf_FP_t) ( + const fapi2::Target&); + +/// @brief Load Core GPTR and Time rings +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_GPTR_TIME_RING - EC target, uint32 +/// pointer to RS4 content
+/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_gptr_time_initf( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_GPTR_TIME_INIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_initf.C b/src/ppe/hwp/core/p9_hcd_core_initf.C new file mode 100644 index 0000000..fad2046 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_initf.C @@ -0,0 +1,95 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_initf.C +/// @brief Core scan init +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// Check for the presence of core FUNC override rings from image; +/// if found, apply; if not, apply core base FUNC rings from image +/// Note: FASTINIT ring (eg CMSK ring) is setup at this point to limit the +/// stumps that participate in FUNC ring scanning (this is new for P9). +/// (TODO to make sure the image build support is in place) +/// Note : if in fused mode, both core rings will be initialized to the same +/// values via multicast scans +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core scan init +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_initf( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + // - load_ring ex_func_core conditional_override=1 + // - load_ring ex_regf_core conditional_override=1 + // - load_ring ex_fary_l2 conditional_override=1 + // - load_ring ex_lbst_core conditional_override=1 + // - load_ring ex_abfa_core conditional_override=1 + // - load_ring ex_cmsk_core conditional_override=1 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_initf.H b/src/ppe/hwp/core/p9_hcd_core_initf.H new file mode 100644 index 0000000..7a9682d --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_initf.H +/// @brief Core scan init +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_INITF_H__ +#define __P9_HCD_CORE_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_initf_FP_t) ( + const fapi2::Target&); + + +/// @brief Core scan init +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_FUNC_RING - EC target, uint32 +/// pointer to RS4 content
+/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_initf( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_INITF_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C new file mode 100644 index 0000000..ccc4c0e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C @@ -0,0 +1,94 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_occ_runtime_scom.C +/// @brief Core OCC runtime SCOMS +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from OCC code that are put somewhere TBD +/// (TODO . revisit with OCC FW team) +/// OCC FW sets up value in the TBD SCOM section +/// This was not leverage in P8 with the demise of CPMs +/// Placeholder at this point +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_occ_runtime_scom.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +#define host_runtime_scom 0 + +//----------------------------------------------------------------------------- +// Procedure: Core OCC runtime SCOMS +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_occ_runtime_scom( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, occ_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching OCC Runtime SCOM routine") + // - bsrd D0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H new file mode 100644 index 0000000..0221370 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_occ_runtime_scom.H +/// @brief Core OCC runtime SCOMS +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ +#define __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_occ_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_occ_runtime_scom_FP_t) ( + const fapi2::Target&); + + +/// @brief Core OCC runtime SCOMS +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem ATTR_CORE_OCC_SCOM_LOC - EC target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_occ_runtime_scom( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_pcb_arb.C b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.C new file mode 100644 index 0000000..4dbf22e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.C @@ -0,0 +1,83 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_pcb_arb.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_pcb_arb.C +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// If CME, +/// 1.Request PCB Mux, via write to PCB_MUX_REQ_C0 @ CCSCR_OR +/// - setBit(5) @ CME_LOCAL_CORE_STOP_CONTROL_REGISTER_OR_0510 +/// 2.Poll for PCB Mux grant, via read from +/// Polled Timeout: ns +/// - getBit() @ +/// Else (SBE), +/// Nop (as the CME is not running in bringing up the first Core) +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_pcb_arb.H" + +//----------------------------------------------------------------------------- +// Constant Definitions: Core Chiplet PCB Arbitration +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_pcb_arb( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_pcb_arb.H b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.H new file mode 100644 index 0000000..4029514 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_pcb_arb.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_pcb_arb.H +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_PCB_ARB_H__ +#define __P9_HCD_CORE_PCB_ARB_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_pcb_arb_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_pcb_arb_FP_t) ( + const fapi2::Target&); + +/// @brief Core Chiplet PCB Arbitration +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_pcb_arb( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_PCB_ARB_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_poweron.C b/src/ppe/hwp/core/p9_hcd_core_poweron.C new file mode 100644 index 0000000..e215c27 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_poweron.C @@ -0,0 +1,84 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_poweron.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_poweron.C +/// @brief Core Chiplet Power-on +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// 1.Command the core PFET controller to power-on, via putscom to CPPM +/// - +/// 2.Check for valid power on completion, via getscom from CPPM +/// Polled Timeout: 100us +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_poweron.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core Chiplet Power-on +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_poweron( + const fapi2::Target& i_target, + const uint32_t i_operation) +{ + +#if 0 + + fapi2::buffer data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_poweron.H b/src/ppe/hwp/core/p9_hcd_core_poweron.H new file mode 100644 index 0000000..970d1e4 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_poweron.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_poweron.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_poweron.H +/// @brief Core Chiplet Power-on +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_POWERON_H__ +#define __P9_HCD_CORE_POWERON_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_poweron_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_poweron_FP_t) ( + const fapi2::Target&, + const uint32_t); + + +/// @brief Core Chiplet Power-on +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_* +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_poweron( + const fapi2::Target& i_target, + const uint32_t i_operation); + + +} // extern C + +#endif // __P9_HCD_CORE_POWERON_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C new file mode 100644 index 0000000..654e24e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C @@ -0,0 +1,165 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_ras_runtime_scom.C +/// @brief FSP/Host run-time SCOMS +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from FSP based PRD, etc that are put on the core image +/// by STOP API calls +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (the SBE case), return +/// Else call the function at the pointer; +/// pointer is filled in by STOP image build +/// Run-time updates from Host code that are put on the core image by +/// STOP API calls +/// Restore Hypervisor, Host PRD, etc. SCOMs +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_ras_runtime_scom.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +#define host_runtime_scom 0 + +//----------------------------------------------------------------------------- +// Procedure: FSP/Host run-time SCOMS +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_ras_runtime_scom( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, sp_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching SP Runtime SCOM routine") + // - bsrd D0 + // - 1: + // + + // Run the SCOM sequence if the SCOM procedure is defined. + // - la A0, host_runtime_scom + // - ld D1, 0, A0 + // - braz D1, 1f + + // Prep P1 + // - setp1_mcreadand D0 +#if 0 + // Disable the AISS to allow the override + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~(BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - ori D0, D0, (BIT(15)) + // - andi D0, D0, ~(BIT(21)) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + // Branch to sub_slw_runtime_scom() + FAPI_INF("Launching Host Runtime SCOM routine") + // - bsrd D1 + + // Prep P1 + // - setp1_mcreadand D0 +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - andi D0, D0, ~(BIT(15)) + // - ori D0, D0, BIT(21) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - ori D0, D0, (BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - bra 2f + // - 1: + // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped + // - setp1_mcreadand D0 +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~BIT(1) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - andi D0, D0, ~(BIT(15)) + // - ori D0, D0, BIT(21) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - ori D0, D0, (BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - 2: + + // If using cv_multicast, we need to set the magic istep number here + // - la A0, p9_sbe_select_ex_control + // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX + // - braz D0, 3f + FAPI_DBG("Setting istep num to magic number because cv_multicast is set") + // - lpcs P1, MBOX_SBEVITAL_0x0005001C + // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) + // - 3: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H new file mode 100644 index 0000000..aca5bc2 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_ras_runtime_scom.H +/// @brief FSP/Host run-time SCOMS +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ +#define __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_ras_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_ras_runtime_scom_FP_t) ( + const fapi2::Target&); + + +/// @brief FSP/Host run-time SCOMS +/// +/// @param [in] i_target TARGET_TYPE_CORE target +// +/// @attr +/// @attritem ATTR_CORE_RAS_SCOM_LOC - EC target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_ras_runtime_scom( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_repair_initf.C b/src/ppe/hwp/core/p9_hcd_core_repair_initf.C new file mode 100644 index 0000000..167c84e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_repair_initf.C @@ -0,0 +1,89 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_repair_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_repair_initf.C +/// @brief Load Repair ring for core +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Load core ring images from that came from MVPD into the image +/// These rings must contain ALL chip customization data. This includes the +/// following: Array Repair and DTS calibration settings +/// Historically this was stored in MVPD keywords are #R, #G. Still stored +/// in MVPD, but SBE image is customized with rings for booting cores +/// at build time +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_repair_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Load Repair ring for core +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_repair_initf( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + // scan chiplet specific ring content + //FAPI_DBG("Scanning EX core REPAIR rings...") + // - load_ring_vec_ex ex_repr_core + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_repair_initf.H b/src/ppe/hwp/core/p9_hcd_core_repair_initf.H new file mode 100644 index 0000000..7c9b831 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_repair_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_repair_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_repair_initf.H +/// @brief Load Repair ring for core +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_REPAIR_INITF_H__ +#define __P9_HCD_CORE_REPAIR_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_repair_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_repair_initf_FP_t) ( + const fapi2::Target&); + + +/// @brief Load Repair ring for core +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_REPAIR_RING - EC target, uint32 +/// pointer to RS4 content +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_repair_initf( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_REPAIR_INITF_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_runinit.C b/src/ppe/hwp/core/p9_hcd_core_runinit.C new file mode 100644 index 0000000..eedc0fe --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_runinit.C @@ -0,0 +1,75 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_runinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_runinit.C +/// @brief execute all core init procedures +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_runinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_runinit( + const fapi2::Target& i_target) +{ + return fapi2::FAPI2_RC_SUCCESS; + +#if 0 + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_runinit.H b/src/ppe/hwp/core/p9_hcd_core_runinit.H new file mode 100644 index 0000000..09881a8 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_runinit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_runinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_runinit.H +/// @brief execute all core init procedures +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_RUNINIT_H__ +#define __P9_HCD_CORE_RUNINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_runinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_runinit_FP_t) ( + const fapi2::Target&); + + +/// @brief Core Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_PROC_CHIP target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_runinit( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_RUNINIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_scomcust.C b/src/ppe/hwp/core/p9_hcd_core_scomcust.C new file mode 100644 index 0000000..11a1c15 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scomcust.C @@ -0,0 +1,83 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scomcust.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scomcust.C +/// @brief Core Customization SCOMs +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Dynamically built (and installed) routine that is inserted by the .XIP +/// Customization. process. (New for P9) (TODO: this part of the process is +/// a placeholder at this point) +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (a potential early value); return +/// Else call the function at the pointer; +/// pointer is filled in by XIP Customization +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_scomcust.H" + +//----------------------------------------------------------------------------- +// Constant Definitions: Core Customization SCOMs +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_scomcust( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_scomcust.H b/src/ppe/hwp/core/p9_hcd_core_scomcust.H new file mode 100644 index 0000000..b9643c6 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scomcust.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scomcust.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scomcust.H +/// @brief Core Customization SCOMs +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_SCOMCUST_H__ +#define __P9_HCD_CORE_SCOMCUST_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_scomcust_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_scomcust_FP_t) ( + const fapi2::Target&); + + +/// @brief Core Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_scomcust( + const fapi2::Target& i_target); + +} // extern C + +#endif // __P9_HCD_CORE_SCOMCUST_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_scominit.C b/src/ppe/hwp/core/p9_hcd_core_scominit.C new file mode 100644 index 0000000..3d4030d --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scominit.C @@ -0,0 +1,160 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scominit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scominit.C +/// @brief Core SCOM Inits +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Apply any coded SCOM initialization to core +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_scominit.H" + + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core SCOM Inits +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_scominit( + const fapi2::Target& i_target) +{ + +#if 0 + fapi2::buffer data; + + /////////////////// + // Core + /////////////////// + + // Force the hardware to think we're in special wakeup so the SCOMs will + // succeed to the core due to the init state of Nap. This does NOT + // influence the PM state machines; only the wire indicating special + // wake-up using the override in PMGP1 + // Bit 6 enables/disables override; bit 8 controls the Special Wake-up + // = sti EX_PMGP1_OR_0x100F0105, P0, BIT(6) | BIT(8) + FAPI_TRY(putScom(i_target, EX_PMGP1_OR_0x100F0105, + fapi2:buffer().insertFromRight<6,3>(0x5))); + // - setp1_mcreadand D0 +#if 0 + // Disable the AISS to allow the override + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~(BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - ori D0, D0, (BIT(15)) + // - andi D0, D0, ~(BIT(21)) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + //CMO-> Should prob reenable AISS here. But carefully... + + // These are dropped in p9_sbe_ex_host_runtime_scom.S + + /////////////////// + // Clock Controller + /////////////////// + + // Set the OPCG_PAD_VALUE to be fast enough to not allow overrun by the + // OHA in for Deep Sleep Exit. Set for 32 cycles (2 x 16) -> 0b010 + FAPI_INF("Setup OPCG_PAD_VALUE for Deep Sleep scanning ...") + // - ld D1, EX_OPCG_CNTL2_0x10030004, P1 + // - andi D1, D1, ~(BITS(49,3)) + // - ori D1, D1, BIT(50) + // - std D1, EX_OPCG_CNTL2_0x10030004, P0 + FAPI_TRY(getScom(i_target, EX_OPCG_CNTL2_0x10030004, data)); + data.insertFromRight<49,3>(0x2); + FAPI_TRY(putScom(i_target, EX_OPCG_CNTL2_0x10030004, data)); + + /////////////////// + // L2 + /////////////////// + + // set L2 inits to force single member mode if required + FAPI_DBG("Configuring L2 single member mode ..."); + // - l2_single_member + + // set L2 inits to disable L3 if required + FAPI_DBG("Configuring L3 disable ..."); + // - l3_setup L3_SETUP_ACTION_DISABLE, L3_SETUP_UNIT_L2 + + /////////////////// + // DTS + /////////////////// + + // As this routine get runs for IPL, Winkle and Sleep, all Digital + // Thermal Sensor setup is done here. + // For the case of Sleep where the L3 DTS is still active, the + // initialization is redone anyway as, while this operation is going on, + // the atomic lock prevents other entities (eg OCC) from accessing it. + // This keep the flows the same. + + // - setp1_mcreadand D0 + FAPI_INF("Initialize DTS function ...") + + // Enable DTS sampling - bit 5 + // Sample Pulse Count - bits(6:9) set to a small number for sim + // Enable loop 1 DTSs (20:22); loop 2 DTSs (24) + // = ld D1, EX_THERM_MODE_REG_0x1005000F, P1 + // = ori D1, D1, (BIT(5)|BITS(6, 4)|BITS(20,3)|BIT(24)) + // = std D1, EX_THERM_MODE_REG_0x1005000F, P0 + FAPI_TRY(getScom(i_target, EX_THERM_MODE_REG_0x1005000F, data)); + data.insertFromRight<5,5>(0x1F).insertFromRight<20,3>(0xF).setBit<24>(); + FAPI_TRY(putScom(i_target, EX_THERM_MODE_REG_0x1005000F, data)); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_scominit.H b/src/ppe/hwp/core/p9_hcd_core_scominit.H new file mode 100644 index 0000000..9cb570a --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scominit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scominit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scominit.H +/// @brief Core SCOM Inits +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_SCOMINIT_H__ +#define __P9_HCD_CORE_SCOMINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_scominit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_scominit_FP_t) ( + const fapi2::Target&); + + +/// @brief Core SCOM Inits +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_scominit( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_SCOMINIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_startclocks.C b/src/ppe/hwp/core/p9_hcd_core_startclocks.C new file mode 100644 index 0000000..012f533 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_startclocks.C @@ -0,0 +1,97 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_startclocks.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_startclocks.C +/// @brief Core Clock Start +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Drop pervasive thold +/// Drop pervasive fence +/// Reset abst clock muxsel, sync muxsel +/// Clear clock controller scan register before start +/// Start arrays + nsl regions +/// Start sl + refresh clock regions +/// Check for clocks started +/// If not, error +/// Check for core xstop (TODO: need for this (?) and then FIR structure in +/// for P9. Note: CME can NOT read Cache FIR) +/// If so, error +/// Clear force align +/// Clear flush mode +/// Check security switch and set trusted boot en bit +/// (TODO: still needed for P9?) +/// Drop the core to cache logical fence +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include +//#include +//will be replaced with real scom address header file +#include "p9_hcd_core_startclocks.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core Clock Start +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_startclocks( + const fapi2::Target& i_target) +{ + +#if 0 + + fapi2::buffer data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/core/p9_hcd_core_startclocks.H b/src/ppe/hwp/core/p9_hcd_core_startclocks.H new file mode 100644 index 0000000..38b6fbd --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_startclocks.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_startclocks.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_startclocks.H +/// @brief Core Clock Start +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_STARTCLOCKS_H__ +#define __P9_HCD_CORE_STARTCLOCKS_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_startclocks_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_startclocks_FP_t) ( + const fapi2::Target&); + +/// @brief Core Clock Start +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_startclocks( + const fapi2::Target& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_STARTCLOCKS_H__ diff --git a/src/ppe/hwp/lib/Makefile b/src/ppe/hwp/lib/Makefile new file mode 100644 index 0000000..360d012 --- /dev/null +++ b/src/ppe/hwp/lib/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/lib/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the common library hardware procedure code. +# See the "libcommonfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/lib +export SUB_OBJDIR = /lib + +include img_defs.mk +include libcommonfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(LIB_OBJECTS)) + +libcommon.a: lib + $(AR) crs $(OBJDIR)/libcommon.a $(OBJDIR)/*.o + +.PHONY: clean lib +lib: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ppe/hwp/lib/libcommonfiles.mk b/src/ppe/hwp/lib/libcommonfiles.mk new file mode 100644 index 0000000..854d71b --- /dev/null +++ b/src/ppe/hwp/lib/libcommonfiles.mk @@ -0,0 +1,53 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/lib/libcommonfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file libcommonfiles.mk +# +# @brief mk for including library common object files +# +# @page ChangeLogs Change Logs +# @section libcommonfiles.mk +# @verbatim +# +# +# Change Log ****************************************************************** +# Flag Defect/Feature User Date Description +# ------ -------------- ---------- ------------ ----------- +# +# @endverbatim +# +########################################################################## +# Object Files +########################################################################## + +LIB-CPP-SOURCES += p9_common_poweronoff.C +LIB-CPP-SOURCES += p9_common_pro_epi_log.C + +LIB-C-SOURCES += +LIB-S-SOURCES += + +LIB_OBJECTS += $(LIB-CPP-SOURCES:.C=.o) +LIB_OBJECTS += $(LIB-C-SOURCES:.c=.o) +LIB_OBJECTS += $(LIB-S-SOURCES:.S=.o) + diff --git a/src/ppe/hwp/lib/p9_common_poweronoff.C b/src/ppe/hwp/lib/p9_common_poweronoff.C new file mode 100644 index 0000000..cd5e6f8 --- /dev/null +++ b/src/ppe/hwp/lib/p9_common_poweronoff.C @@ -0,0 +1,71 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/lib/p9_common_poweronoff.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_poweronoff.C +/// @brief common procedure for power on/off +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_common_poweronoff.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_common_poweronoff( + const fapi2::Target& i_target, + int i_operation) +{ + return fapi2::FAPI2_RC_SUCCESS; + + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/lib/p9_common_poweronoff.H b/src/ppe/hwp/lib/p9_common_poweronoff.H new file mode 100644 index 0000000..a5bd036 --- /dev/null +++ b/src/ppe/hwp/lib/p9_common_poweronoff.H @@ -0,0 +1,68 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/lib/p9_common_poweronoff.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_poweronoff.H +/// @brief common procedure for power on/off +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_COMMON_POWERONOFF_H__ +#define __P9_COMMON_POWERONOFF_H__ + +extern "C" +{ + +/// @typedef p9_common_proweronoff_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_common_proweronoff_FP_t) ( + const fapi2::Target&, + int); + + +/// @brief common procedure for power on/off +/// +/// @param [in] i_target TARGET_TYPE_EQ|TARGET_TYPE_CORE target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_TIMING - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_common_proweronoff( + const fapi2::Target& i_target, + int i_operation); + + +} // extern C + +#endif // __P9_COMMON_POWERONOFF_H__ diff --git a/src/ppe/hwp/lib/p9_common_pro_epi_log.C b/src/ppe/hwp/lib/p9_common_pro_epi_log.C new file mode 100644 index 0000000..33237cd --- /dev/null +++ b/src/ppe/hwp/lib/p9_common_pro_epi_log.C @@ -0,0 +1,70 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/lib/p9_common_pro_epi_log.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_pro_epi_log.C +/// @brief common procedure prologue/epilogue routines +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +//#include +//will be replaced with real scom address header file +#include "p9_common_pro_epi_log.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_common_pro_epi_log( + const fapi2::Target& i_target, + int i_operation) +{ + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/lib/p9_common_pro_epi_log.H b/src/ppe/hwp/lib/p9_common_pro_epi_log.H new file mode 100644 index 0000000..b119b37 --- /dev/null +++ b/src/ppe/hwp/lib/p9_common_pro_epi_log.H @@ -0,0 +1,68 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/lib/p9_common_pro_epi_log.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_pro_epi_log.H +/// @brief common procedure prologue/epilogue routines +/// +/// *HWP HWP Owner : David Du +/// *HWP FW Owner : Reshmi Nair +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_COMMON_PRO_EPI_LOG_H__ +#define __P9_COMMON_PRO_EPI_LOG_H__ + +extern "C" +{ + +/// @typedef p9_common_pro_epi_log_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_common_pro_epi_log_FP_t) ( + const fapi2::Target&, + int); + + +/// @brief common procedure prologue/epilogue routines +/// +/// @param [in] i_target TARGET_TYPE_EQ|TARGET_TYPE_CORE target +/// @param [in] i_operation ENUM(PROLOG, EPILOG) +/// +/// @attr +/// @attritem ATTR_EX_PARIAL_GOOD - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_common_pro_epi_log( + const fapi2::Target& i_target, + int i_operation); + + +} // extern C + +#endif // __P9_COMMON_PRO_EPI_LOG_H__ diff --git a/src/ppe/hwp/nest/.empty b/src/ppe/hwp/nest/.empty new file mode 100644 index 0000000..e69de29 diff --git a/src/ppe/hwp/perv/.empty b/src/ppe/hwp/perv/.empty new file mode 100644 index 0000000..e69de29 diff --git a/src/ppe/hwp/perv/Makefile b/src/ppe/hwp/perv/Makefile new file mode 100644 index 0000000..68a803f --- /dev/null +++ b/src/ppe/hwp/perv/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/perv/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the core hardware procedure code. See the +# "pervfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/perv +export SUB_OBJDIR = /perv + +include img_defs.mk +include pervfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(PERV_OBJECTS)) + +libperv.a: perv + $(AR) crs $(OBJDIR)/libperv.a $(OBJDIR)/*.o + +.PHONY: clean perv +perv: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ppe/hwp/perv/p9_sbe_attr_setup.C b/src/ppe/hwp/perv/p9_sbe_attr_setup.C new file mode 100644 index 0000000..cc08372 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_attr_setup.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_attr_setup.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_attr_setup.C +/// +/// @brief If and only if scratch registers are non-zero, HWP will read the contents of the scratch registers and call FAPI2 APIs to set the values into the corresponding platform ATTR +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_attr_setup.H" +fapi2::ReturnCode p9_sbe_attr_setup(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_attr_setup: Entering ..."); + + FAPI_DBG("p9_sbe_attr_setup: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_attr_setup.H b/src/ppe/hwp/perv/p9_sbe_attr_setup.H new file mode 100644 index 0000000..d392969 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_attr_setup.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_attr_setup.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_attr_setup.H +/// +/// @brief If and only if scratch registers are non-zero, HWP will read the contents of the scratch registers and call FAPI2 APIs to set the values into the corresponding platform ATTR +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ATTR_SETUP_H_ +#define _P9_SBE_ATTR_SETUP_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_attr_setup_FP_t)(const + fapi2::Target &); + +/// @brief --Setting All Mailbox scratch register 1, 2, 3, 4, 5, 6, 7, 8 +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_attr_setup(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_check_master.C b/src/ppe/hwp/perv/p9_sbe_check_master.C new file mode 100644 index 0000000..b348bdf --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_check_master.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_check_master.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master.C +/// +/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_check_master.H" +fapi2::ReturnCode p9_sbe_check_master(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_check_master: Entering ..."); + + FAPI_DBG("p9_sbe_check_master: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_check_master.H b/src/ppe/hwp/perv/p9_sbe_check_master.H new file mode 100644 index 0000000..04a1748 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_check_master.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_check_master.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master.H +/// +/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHECK_MASTER_H_ +#define _P9_SBE_CHECK_MASTER_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_check_master_FP_t)(const + fapi2::Target &); + +/// @brief If master continue, else enable runtime chipOps +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_check_master(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_enable_seeprom.C b/src/ppe/hwp/perv/p9_sbe_enable_seeprom.C new file mode 100644 index 0000000..eab78e2 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_enable_seeprom.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_enable_seeprom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_enable_seeprom.C +/// +/// @brief SBE enable SEEPROM (runs from OTPROM) +/// +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_enable_seeprom.H" +fapi2::ReturnCode p9_sbe_enable_seeprom(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_enable_seeprom: Entering ..."); + + FAPI_DBG("p9_sbe_enable_seeprom: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_enable_seeprom.H b/src/ppe/hwp/perv/p9_sbe_enable_seeprom.H new file mode 100644 index 0000000..e74e114 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_enable_seeprom.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_enable_seeprom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_enable_seeprom.H +/// +/// @brief SBE enable SEEPROM (runs from OTPROM) +/// +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ENABLE_SEEPROM_H_ +#define _P9_SBE_ENABLE_SEEPROM_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_enable_seeprom_FP_t)( + const fapi2::Target &); + +/// @brief -- Check SBE Vital Register for selected SEEPROM image +/// -- Update SBE FI2C_E0_PARAM register +/// -- Check for valid SEEPROM image +/// -- Branch to SEEPROM +/// +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_enable_seeprom(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_lpc_init.C b/src/ppe/hwp/perv/p9_sbe_lpc_init.C new file mode 100644 index 0000000..533bad3 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_lpc_init.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_lpc_init.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_lpc_init.C +/// +/// @brief Requirement from the bootloader is that it only uses MMIOs to LPC master, not Xscom +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_lpc_init.H" +fapi2::ReturnCode p9_sbe_lpc_init(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_lpc_init: Entering ..."); + + FAPI_DBG("p9_sbe_lpc_init: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_lpc_init.H b/src/ppe/hwp/perv/p9_sbe_lpc_init.H new file mode 100644 index 0000000..859f7bf --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_lpc_init.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_lpc_init.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_lpc_init.H +/// +/// @brief Requirement from the bootloader is that it only uses MMIOs to LPC master, not Xscom +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_LPC_INIT_H_ +#define _P9_SBE_LPC_INIT_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_lpc_init_FP_t)(const + fapi2::Target &); + +/// @brief PerfoPerform scoms to setup LPC bus +/// -- Move the LPC clock to external input +/// Pull the LPC unit out of reset +/// Set LPC BAR -- hardcoded like Xscom BAR +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_lpc_init(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_nest_arrayinit.C b/src/ppe/hwp/perv/p9_sbe_nest_arrayinit.C new file mode 100644 index 0000000..141f29a --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_arrayinit.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_arrayinit.C +/// +/// @brief array init for nest chiplet arrays +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_arrayinit.H" +fapi2::ReturnCode p9_sbe_nest_arrayinit(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_nest_arrayinit: Entering ..."); + + FAPI_DBG("p9_sbe_nest_arrayinit: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_nest_arrayinit.H b/src/ppe/hwp/perv/p9_sbe_nest_arrayinit.H new file mode 100644 index 0000000..33deab2 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_arrayinit.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_arrayinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_arrayinit.H +/// +/// @brief array init for nest chiplet arrays +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_ARRAYINIT_H_ +#define _P9_SBE_NEST_ARRAYINIT_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_nest_arrayinit_FP_t)( + const fapi2::Target &); + +/// @brief --Run arrayinit on all enabled chiplets +/// --Scan flush 0 to all rings except GPTR, Time, Repair on all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_arrayinit(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.C b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.C new file mode 100644 index 0000000..d60414b --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_chiplet_init.C +/// +/// @brief proc sbe nest chiplet init +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_chiplet_init.H" +fapi2::ReturnCode p9_sbe_nest_chiplet_init(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_nest_chiplet_init: Entering ..."); + + FAPI_DBG("p9_sbe_nest_chiplet_init: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.H b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.H new file mode 100644 index 0000000..795e3a6 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_chiplet_init.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_chiplet_init.H +/// +/// @brief proc sbe nest chiplet init +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_CHIPLET_INIT_H_ +#define _P9_SBE_NEST_CHIPLET_INIT_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_nest_chiplet_init_FP_t)( + const fapi2::Target &); + +/// @brief --Scan 0 all rings (except time, repair, gptr) on all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_chiplet_init(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.C b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.C new file mode 100644 index 0000000..4a8626d --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_chiplet_reset.C +/// +/// @brief proc nest chiplet reset +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_chiplet_reset.H" +fapi2::ReturnCode p9_sbe_nest_chiplet_reset(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_nest_chiplet_reset: Entering ..."); + + FAPI_DBG("p9_sbe_nest_chiplet_reset: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.H b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.H new file mode 100644 index 0000000..e9922eb --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_chiplet_reset.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_chiplet_reset.H +/// +/// @brief proc nest chiplet reset +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_CHIPLET_RESET_H_ +#define _P9_SBE_NEST_CHIPLET_RESET_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_nest_chiplet_reset_FP_t)( + const fapi2::Target &); + +/// @brief Reset Nest chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_chiplet_reset(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.C b/src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.C new file mode 100644 index 0000000..c06d950 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_gptr_time_repr_initf.C +/// +/// @brief proc sbe nest gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_gptr_time_repr_initf.H" +fapi2::ReturnCode p9_sbe_nest_gptr_time_repr_initf(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_nest_gptr_time_repr_initf: Entering ..."); + + FAPI_DBG("p9_sbe_nest_gptr_time_repr_initf: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.H b/src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.H new file mode 100644 index 0000000..b37145b --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_gptr_time_repr_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_gptr_time_repr_initf.H +/// +/// @brief proc sbe nest gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_GPTR_TIME_REPR_INITF_H_ +#define _P9_SBE_NEST_GPTR_TIME_REPR_INITF_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_nest_gptr_time_repr_initf_FP_t)( + const fapi2::Target &); + +/// @brief Scan 0 all rings on all enabled chiplets (except for TP) +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_gptr_time_repr_initf(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_nest_initf.C b/src/ppe/hwp/perv/p9_sbe_nest_initf.C new file mode 100644 index 0000000..c8bd4a7 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_initf.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_initf.C +/// +/// @brief proc_sbe_nest_initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_initf.H" +fapi2::ReturnCode p9_sbe_nest_initf(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_nest_initf: Entering ..."); + + FAPI_DBG("p9_sbe_nest_initf: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_nest_initf.H b/src/ppe/hwp/perv/p9_sbe_nest_initf.H new file mode 100644 index 0000000..2add6ac --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_initf.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_initf.H +/// +/// @brief proc_sbe_nest_initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_INITF_H_ +#define _P9_SBE_NEST_INITF_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_nest_initf_FP_t)(const + fapi2::Target &); + +/// @brief apply init file +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_initf(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_nest_startclocks.C b/src/ppe/hwp/perv/p9_sbe_nest_startclocks.C new file mode 100644 index 0000000..d44835d --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_startclocks.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_startclocks.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_startclocks.C +/// +/// @brief start clocks for nest chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_startclocks.H" +fapi2::ReturnCode p9_sbe_nest_startclocks(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_nest_startclocks: Entering ..."); + + FAPI_DBG("p9_sbe_nest_startclocks: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_nest_startclocks.H b/src/ppe/hwp/perv/p9_sbe_nest_startclocks.H new file mode 100644 index 0000000..e4644c9 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_nest_startclocks.H @@ -0,0 +1,68 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_nest_startclocks.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_startclocks.H +/// +/// @brief start clocks for nest chiplets +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_STARTCLOCKS_H_ +#define _P9_SBE_NEST_STARTCLOCKS_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_nest_startclocks_FP_t)( + const fapi2::Target &); + +/// @brief --drop vital fence +/// --reset abstclk muxsel and syncclk muxsel +/// --Module align chiplets +/// --Module clock start stop +/// --Check clock stat SL, NSL , ARY +/// --drop chiplet fence +/// --check checkstop register +/// --clear flush inhibit to go into flush mode +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_startclocks(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_npll_initf.C b/src/ppe/hwp/perv/p9_sbe_npll_initf.C new file mode 100644 index 0000000..d40f141 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_npll_initf.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_npll_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_initf.C +/// +/// @brief apply initfile for level 0 & 1 PLLs +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_npll_initf.H" +fapi2::ReturnCode p9_sbe_npll_initf(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_npll_initf: Entering ..."); + + FAPI_DBG("p9_sbe_npll_initf: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_npll_initf.H b/src/ppe/hwp/perv/p9_sbe_npll_initf.H new file mode 100644 index 0000000..8445de1 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_npll_initf.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_npll_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_initf.H +/// +/// @brief apply initfile for level 0 & 1 PLLs +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NPLL_INITF_H_ +#define _P9_SBE_NPLL_INITF_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_npll_initf_FP_t)(const + fapi2::Target &); + +/// @brief --run scan0 module (scan region = PLL, scan_types = GPTR) +/// --run scan0 module (scan region = PLL, scan_types = BNDY/FUNC) +/// --Scan initialize PLL BNDY chain (chiplet = PERV, scan ring = PLL, scan type = BNDY) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_npll_initf(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_npll_setup.C b/src/ppe/hwp/perv/p9_sbe_npll_setup.C new file mode 100644 index 0000000..1a66606 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_npll_setup.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_npll_setup.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_setup.C +/// +/// @brief scan initialize level 0 & 1 PLLs +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_npll_setup.H" +fapi2::ReturnCode p9_sbe_npll_setup(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_npll_setup: Entering ..."); + + FAPI_DBG("p9_sbe_npll_setup: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_npll_setup.H b/src/ppe/hwp/perv/p9_sbe_npll_setup.H new file mode 100644 index 0000000..bcc5f01 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_npll_setup.H @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_npll_setup.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_setup.H +/// +/// @brief scan initialize level 0 & 1 PLLs +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NPLL_SETUP_H_ +#define _P9_SBE_NPLL_SETUP_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_npll_setup_FP_t)(const + fapi2::Target &); + +/// @brief --Release PLL test enable for SS, Filt & NEST PLLs +/// --Release SS PLL reset0 +/// --check SS PLL lock +/// --Release SS PLL bypass0 +/// --Release Filter PLL reset1 +/// --check PLL lock for Filter PLLs +/// --Release Filter PLL bypass signals +/// --Switch MC meshs to Nest mesh +/// --Release test_pll_bypass2 +/// --Release Tank PLL reset2 +/// --check Nest PLL lock +/// --Release Tank PLL bypass2 +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_npll_setup(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_select_ex.C b/src/ppe/hwp/perv/p9_sbe_select_ex.C new file mode 100644 index 0000000..1976840 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_select_ex.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_select_ex.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_select_ex.C +/// +/// @brief proc sbe select ex +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_select_ex.H" +fapi2::ReturnCode p9_sbe_select_ex(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_select_ex: Entering ..."); + + FAPI_DBG("p9_sbe_select_ex: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_select_ex.H b/src/ppe/hwp/perv/p9_sbe_select_ex.H new file mode 100644 index 0000000..a62d1dd --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_select_ex.H @@ -0,0 +1,66 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_select_ex.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_select_ex.H +/// +/// @brief proc sbe select ex +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_SELECT_EX_H_ +#define _P9_SBE_SELECT_EX_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_select_ex_FP_t)(const + fapi2::Target &); + +/// @brief ATTR will indicate single core or all +/// Use the partial good info and ATTR to find the first good core +/// For selected master EQ and Core +/// -- Turn on chiplet enable +/// Write selected EQ/Core mask into OCC complex +/// -- This is the "master record " of the enabled cores/quad in the system +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_select_ex(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_arrayinit.C b/src/ppe/hwp/perv/p9_sbe_tp_arrayinit.C new file mode 100644 index 0000000..0371235 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_arrayinit.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_arrayinit.C +/// +/// @brief SBE PRV Array Init Procedure +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_arrayinit.H" +fapi2::ReturnCode p9_sbe_tp_arrayinit(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_arrayinit: Entering ..."); + + FAPI_DBG("p9_sbe_tp_arrayinit: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_arrayinit.H b/src/ppe/hwp/perv/p9_sbe_tp_arrayinit.H new file mode 100644 index 0000000..5ece4e4 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_arrayinit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_arrayinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_arrayinit.H +/// +/// @brief SBE PRV Array Init Procedure +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_ARRAYINIT_H_ +#define _P9_SBE_TP_ARRAYINIT_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_arrayinit_FP_t)(const + fapi2::Target &); + +/// @brief -- Array Init for PRV Cplt +/// -- Scan0 of PRV Chiplet (except PIB/PCB) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_arrayinit(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C new file mode 100644 index 0000000..4756b0b --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init1.C +/// +/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init1.H" +fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_chiplet_init1: Entering ..."); + + FAPI_DBG("p9_sbe_tp_chiplet_init1: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H new file mode 100644 index 0000000..601c167 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_init1.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init1.H +/// +/// @brief IPL STEP 2.3: SBE TP Chiplet Init 1 :: Releases PCB Reset, Sets TP chiplet enable, Drops Perv chiplet fence +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT1_H_ +#define _P9_SBE_TP_CHIPLET_INIT1_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)( + const fapi2::Target &); + +/// @brief DESCRIPTION -- Drop VSS2VIO fence +/// -- Releases PCB reset +/// -- Sets PRV Chiplet Enable +/// -- Drops PRV Chiplet fence enable +/// -- Drop Global Endpoint Reset +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.C new file mode 100644 index 0000000..36ebf0f --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init2.C +/// +/// @brief IPL STEP 2.10 : SBE TP Chiplet Init2 :: Run scan 0 module for pervasive +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init2.H" +fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_chiplet_init2: Entering ..."); + + FAPI_DBG("p9_sbe_tp_chiplet_init2: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.H new file mode 100644 index 0000000..d37e8be --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_init2.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init2.H +/// +/// @brief IPL STEP 2.10 : SBE TP Chiplet Init2 :: Run scan 0 module for pervasive +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT2_H_ +#define _P9_SBE_TP_CHIPLET_INIT2_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init2_FP_t)( + const fapi2::Target &); + +/// @brief -- Initialize TP Hangcounter 6 +/// -- Scan Repair, Time and GPTR for PRV Chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.C new file mode 100644 index 0000000..80cb27e --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init3.C +/// +/// @brief SBE Pervasive Init Procedure 3 +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init3.H" +fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_chiplet_init3: Entering ..."); + + FAPI_DBG("p9_sbe_tp_chiplet_init3: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.H new file mode 100644 index 0000000..25c1c2e --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.H @@ -0,0 +1,68 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_init3.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init3.H +/// +/// @brief SBE Pervasive Init Procedure 3 +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT3_H_ +#define _P9_SBE_TP_CHIPLET_INIT3_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init3_FP_t)( + const fapi2::Target &); + +/// @brief -- Switches PRV Chiplet OOB mux +/// -- Reset PCB Master Interrupt Register +/// -- Drop Pervasive and OCC2PIB Fence in GP0 (bits 19 & 63) +/// --"Clock Start" command (all other clk domains) +/// -- Clear force_align in chiplet GP0 +/// -- Clear flushmode_inhibit in chiplet GP0 +/// -- Drop FSI fence 5 (checkstop, interrupt conditions) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C new file mode 100644 index 0000000..bc90079 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_reset.C +/// +/// @brief IPL STEP 2.8 : SBE TP Chiplet Reset :: setup hangcounter 6 for TP chiplet +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_reset.H" +fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_chiplet_reset: Entering ..."); + + FAPI_DBG("p9_sbe_tp_chiplet_reset: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H new file mode 100644 index 0000000..9f3c7ae --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_chiplet_reset.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_reset.H +/// +/// @brief IPL STEP 2.8 : SBE TP Chiplet Reset :: setup hangcounter 6 for TP chiplet +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_RESET_H_ +#define _P9_SBE_TP_CHIPLET_RESET_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_reset_FP_t)( + const fapi2::Target &); + +/// @brief --Setup hang counter for PCB slaves/master +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C b/src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C new file mode 100644 index 0000000..57ebc5f --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_repr_initf.C +/// +/// @brief proc sbe tp gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_gptr_time_repr_initf.H" +fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Entering ..."); + + FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H b/src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H new file mode 100644 index 0000000..43e777a --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_repr_initf.H +/// +/// @brief proc sbe tp gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_ +#define _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_gptr_time_repr_initf_FP_t)( + const fapi2::Target &); + +/// @brief --Load Scan Repair, Time and GPTR for TP Chiplet +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_initf.C b/src/ppe/hwp/perv/p9_sbe_tp_initf.C new file mode 100644 index 0000000..908cfad --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_initf.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_initf.C +/// +/// @brief TP chiplet scaninits for the TP rings +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_initf.H" +fapi2::ReturnCode p9_sbe_tp_initf(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_initf: Entering ..."); + + FAPI_DBG("p9_sbe_tp_initf: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_initf.H b/src/ppe/hwp/perv/p9_sbe_tp_initf.H new file mode 100644 index 0000000..56c2cd1 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_initf.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_initf.H +/// +/// @brief TP chiplet scaninits for the TP rings +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_INITF_H_ +#define _P9_SBE_TP_INITF_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_initf_FP_t)(const + fapi2::Target &); + +/// @brief -- This doesn't include the gptr/time/repair rings, +/// -- since they are scanned in tp_chiplet_init2. +/// -- This doesn't include the net/pib/fuse rings, +/// -- since they are used by the SBE hardware itself. +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_initf(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_ld_image.C b/src/ppe/hwp/perv/p9_sbe_tp_ld_image.C new file mode 100644 index 0000000..2741796 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_ld_image.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_ld_image.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_ld_image.C +/// +/// @brief Proc SBE load Image +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_ld_image.H" +fapi2::ReturnCode p9_sbe_tp_ld_image(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_ld_image: Entering ..."); + + FAPI_DBG("p9_sbe_tp_ld_image: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_ld_image.H b/src/ppe/hwp/perv/p9_sbe_tp_ld_image.H new file mode 100644 index 0000000..3e13af6 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_ld_image.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_ld_image.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_ld_image.H +/// +/// @brief Proc SBE load Image +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_LD_IMAGE_H_ +#define _P9_SBE_TP_LD_IMAGE_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_ld_image_FP_t)(const + fapi2::Target &); + +/// @brief This procedure copies the .pibmem0 section of image from SEEPROM to the PIBMEM. +/// The pibmem0 section contains the PORE branch table (error handlers) used for the majority of the SEEPROM IPL as well as +/// performance sensitive routines such as the decompression-scan routine and the LCO loader. +/// Once the image is loaded then the error handlers are switched to +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_ld_image(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_sbe_tp_switch_gears.C b/src/ppe/hwp/perv/p9_sbe_tp_switch_gears.C new file mode 100644 index 0000000..dc9cb47 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_switch_gears.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_switch_gears.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_switch_gears.C +/// +/// @brief SBE switch gears Procedure +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_switch_gears.H" +fapi2::ReturnCode p9_sbe_tp_switch_gears(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_switch_gears: Entering ..."); + + FAPI_DBG("p9_sbe_tp_switch_gears: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_sbe_tp_switch_gears.H b/src/ppe/hwp/perv/p9_sbe_tp_switch_gears.H new file mode 100644 index 0000000..3a7e893 --- /dev/null +++ b/src/ppe/hwp/perv/p9_sbe_tp_switch_gears.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_sbe_tp_switch_gears.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_switch_gears.H +/// +/// @brief SBE switch gears Procedure +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_SWITCH_GEARS_H_ +#define _P9_SBE_TP_SWITCH_GEARS_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_sbe_tp_switch_gears_FP_t)( + const fapi2::Target &); + +/// @brief -- Calls the gear switcher procedure from PIBMEM +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_switch_gears(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_select_boot_master.C b/src/ppe/hwp/perv/p9_select_boot_master.C new file mode 100644 index 0000000..b849a4f --- /dev/null +++ b/src/ppe/hwp/perv/p9_select_boot_master.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_select_boot_master.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_select_boot_master.C +/// +/// @brief Select Boot Master +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_select_boot_master.H" +fapi2::ReturnCode p9_select_boot_master(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_select_boot_master: Entering ..."); + + FAPI_DBG("p9_select_boot_master: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_select_boot_master.H b/src/ppe/hwp/perv/p9_select_boot_master.H new file mode 100644 index 0000000..201fec0 --- /dev/null +++ b/src/ppe/hwp/perv/p9_select_boot_master.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_select_boot_master.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_select_boot_master.H +/// +/// @brief Select Boot Master +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SELECT_BOOT_MASTER_H_ +#define _P9_SELECT_BOOT_MASTER_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_select_boot_master_FP_t)( + const fapi2::Target &); + +/// @brief --Select Master Chip +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_select_boot_master(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_select_clock_mux.C b/src/ppe/hwp/perv/p9_select_clock_mux.C new file mode 100644 index 0000000..c6482cf --- /dev/null +++ b/src/ppe/hwp/perv/p9_select_clock_mux.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_select_clock_mux.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_select_clock_mux.C +/// +/// @brief proc select clock mux +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_select_clock_mux.H" +fapi2::ReturnCode p9_select_clock_mux(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_select_clock_mux: Entering ..."); + + FAPI_DBG("p9_select_clock_mux: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_select_clock_mux.H b/src/ppe/hwp/perv/p9_select_clock_mux.H new file mode 100644 index 0000000..94fa7e1 --- /dev/null +++ b/src/ppe/hwp/perv/p9_select_clock_mux.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_select_clock_mux.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_select_clock_mux.H +/// +/// @brief proc select clock mux +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SELECT_CLOCK_MUX_H_ +#define _P9_SELECT_CLOCK_MUX_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_select_clock_mux_FP_t)(const + fapi2::Target &); + +/// @brief Select internal clock mux to drive the memory clocks off of +/// Flips all bits needed for clock routing (processor only), centaur is done later in p9_cen_ref_clk_enable +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_select_clock_mux(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_set_fsi_gp_shadow.C b/src/ppe/hwp/perv/p9_set_fsi_gp_shadow.C new file mode 100644 index 0000000..ff32cc0 --- /dev/null +++ b/src/ppe/hwp/perv/p9_set_fsi_gp_shadow.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_set_fsi_gp_shadow.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_set_fsi_gp_shadow.C +/// +/// @brief --IPL step 0.8 proc_prep_ipl +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_set_fsi_gp_shadow.H" +fapi2::ReturnCode p9_set_fsi_gp_shadow(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_set_fsi_gp_shadow: Entering ..."); + + FAPI_DBG("p9_set_fsi_gp_shadow: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_set_fsi_gp_shadow.H b/src/ppe/hwp/perv/p9_set_fsi_gp_shadow.H new file mode 100644 index 0000000..c08c3f3 --- /dev/null +++ b/src/ppe/hwp/perv/p9_set_fsi_gp_shadow.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_set_fsi_gp_shadow.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_set_fsi_gp_shadow.H +/// +/// @brief --IPL step 0.8 proc_prep_ipl +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SET_FSI_GP_SHADOW_H_ +#define _P9_SET_FSI_GP_SHADOW_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_set_fsi_gp_shadow_FP_t)(const + fapi2::Target &); + +/// @brief --update ROOT CTRL shadows if needed +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_set_fsi_gp_shadow(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_setup_clock_term.C b/src/ppe/hwp/perv/p9_setup_clock_term.C new file mode 100644 index 0000000..0a62a24 --- /dev/null +++ b/src/ppe/hwp/perv/p9_setup_clock_term.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_setup_clock_term.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_setup_clock_term.C +/// +/// @brief proc setup clock term +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_setup_clock_term.H" +fapi2::ReturnCode p9_setup_clock_term(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_setup_clock_term: Entering ..."); + + FAPI_DBG("p9_setup_clock_term: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_setup_clock_term.H b/src/ppe/hwp/perv/p9_setup_clock_term.H new file mode 100644 index 0000000..f49bb74 --- /dev/null +++ b/src/ppe/hwp/perv/p9_setup_clock_term.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_setup_clock_term.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_setup_clock_term.H +/// +/// @brief proc setup clock term +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SETUP_CLOCK_TERM_H_ +#define _P9_SETUP_CLOCK_TERM_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_setup_clock_term_FP_t)(const + fapi2::Target &); + +/// @brief Setup the clock termination correctly for system/chip type +/// Since this is the first procedure run against the chips it also clears the GP write protect +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_setup_clock_term(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_setup_sbe_config.C b/src/ppe/hwp/perv/p9_setup_sbe_config.C new file mode 100644 index 0000000..68b0446 --- /dev/null +++ b/src/ppe/hwp/perv/p9_setup_sbe_config.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_setup_sbe_config.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_setup_sbe_config.C +/// +/// @brief proc setup sbe config +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_setup_sbe_config.H" +fapi2::ReturnCode p9_setup_sbe_config(const + fapi2::Target & i_target_chip) +{ + FAPI_DBG("p9_setup_sbe_config: Entering ..."); + + FAPI_DBG("p9_setup_sbe_config: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_setup_sbe_config.H b/src/ppe/hwp/perv/p9_setup_sbe_config.H new file mode 100644 index 0000000..5c4521b --- /dev/null +++ b/src/ppe/hwp/perv/p9_setup_sbe_config.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_setup_sbe_config.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_setup_sbe_config.H +/// +/// @brief proc setup sbe config +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SETUP_SBE_CONFIG_H_ +#define _P9_SETUP_SBE_CONFIG_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_setup_sbe_config_FP_t)(const + fapi2::Target &); + +/// @brief update mailbox with boot parameters +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_setup_sbe_config(const + fapi2::Target & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/p9_start_cbs.C b/src/ppe/hwp/perv/p9_start_cbs.C new file mode 100644 index 0000000..fdec2cc --- /dev/null +++ b/src/ppe/hwp/perv/p9_start_cbs.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_start_cbs.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_start_cbs.C +/// +/// @brief Start CBS : Trigger CBS +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_start_cbs.H" +fapi2::ReturnCode p9_start_cbs(const fapi2::Target + & i_target_chip) +{ + FAPI_DBG("p9_start_cbs: Entering ..."); + + FAPI_DBG("p9_start_cbs: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/ppe/hwp/perv/p9_start_cbs.H b/src/ppe/hwp/perv/p9_start_cbs.H new file mode 100644 index 0000000..7e89907 --- /dev/null +++ b/src/ppe/hwp/perv/p9_start_cbs.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/perv/p9_start_cbs.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_start_cbs.H +/// +/// @brief Start CBS : Trigger CBS +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal +// *HWP FW Owner : Brian Silver +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_START_CBS_H_ +#define _P9_START_CBS_H_ + + +#include + + +typedef fapi2::ReturnCode (*p9_start_cbs_FP_t)(const + fapi2::Target &); + +/// @brief --check/wait for VDN_PGOOD = 1 +/// --check for OSC ok +/// --check for VDD (VDD status check) +/// --start CBS(CBS runs thru default path) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_start_cbs(const fapi2::Target + & i_target_chip); +} + +#endif diff --git a/src/ppe/hwp/perv/pervasive_attributes.xml b/src/ppe/hwp/perv/pervasive_attributes.xml new file mode 100644 index 0000000..f49ed7a --- /dev/null +++ b/src/ppe/hwp/perv/pervasive_attributes.xml @@ -0,0 +1,149 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ATTR_BOOT_FREQ + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_CHIP_REGIONS_TO_ENABLE + TARGET_TYPE_PROC_CHIP + + uint32 + + + + ATTR_CHIP_UNIT_POS + TARGET_TYPE_PERV,TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_ECID + TARGET_TYPE_PROC_CHIP + + uint64 + + + + ATTR_EC_GARD + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_EQ_GARD + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_I2C_BUS_DIV_NEST + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_I2C_BUS_DIV_REF + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_MC_SYNC_MODE + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_NEST_PLL_BUCKET + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_PROC_PB_BNDY_DMIPLL_DATA + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_PROC_PERV_BNDY_PLL_DATA + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS + TARGET_TYPE_PROC_CHIP + + uint32 + + + + ATTR_SBE_SEEPROM_I2C_PORT + TARGET_TYPE_PROC_CHIP + + uint32 + + + + ATTR_VCS_BOOT_VOLTAGE + TARGET_TYPE_PROC_CHIP + + uint8 + + + + ATTR_VDD_BOOT_VOLTAGE + TARGET_TYPE_PROC_CHIP + + uint8 + + + diff --git a/src/ppe/hwp/perv/pervfiles.mk b/src/ppe/hwp/perv/pervfiles.mk new file mode 100644 index 0000000..c99113c --- /dev/null +++ b/src/ppe/hwp/perv/pervfiles.mk @@ -0,0 +1,74 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/perv/pervfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file pervfiles.mk +# +# @brief mk for including perv object files +# +# @page ChangeLogs Change Logs +# @section pervfiles.mk +# @verbatim +# +# @endverbatim +# +########################################################################## +# Object Files +########################################################################## + +PERV-CPP-SOURCES = p9_sbe_setup_evid.C +PERV-CPP-SOURCES +=p9_sbe_attr_setup.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C +PERV-CPP-SOURCES +=p9_sbe_check_master.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C +PERV-CPP-SOURCES +=p9_sbe_enable_seeprom.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C +PERV-CPP-SOURCES +=p9_sbe_lpc_init.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_reset.C +PERV-CPP-SOURCES +=p9_sbe_nest_arrayinit.C +PERV-CPP-SOURCES +=p9_sbe_tp_gptr_time_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_nest_chiplet_init.C +PERV-CPP-SOURCES +=p9_sbe_tp_initf.C +PERV-CPP-SOURCES +=p9_sbe_nest_chiplet_reset.C +PERV-CPP-SOURCES +=p9_sbe_tp_ld_image.C +PERV-CPP-SOURCES +=p9_sbe_nest_gptr_time_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_tp_switch_gears.C +PERV-CPP-SOURCES +=p9_sbe_nest_initf.C +PERV-CPP-SOURCES +=p9_select_boot_master.C +PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C +PERV-CPP-SOURCES +=p9_select_clock_mux.C +PERV-CPP-SOURCES +=p9_sbe_npll_initf.C +PERV-CPP-SOURCES +=p9_set_fsi_gp_shadow.C +PERV-CPP-SOURCES +=p9_sbe_npll_setup.C +PERV-CPP-SOURCES +=p9_setup_clock_term.C +PERV-CPP-SOURCES +=p9_sbe_select_ex.C +PERV-CPP-SOURCES +=p9_setup_sbe_config.C +PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C +PERV-CPP-SOURCES +=p9_start_cbs.C + +PERV-C-SOURCES = +PERV-S-SOURCES = + +PERV_OBJECTS += $(PERV-CPP-SOURCES:.C=.o) +PERV_OBJECTS += $(PERV-C-SOURCES:.c=.o) +PERV_OBJECTS += $(PERV-S-SOURCES:.S=.o) diff --git a/src/ppe/hwp/utils/.empty b/src/ppe/hwp/utils/.empty new file mode 100644 index 0000000..e69de29 diff --git a/src/ppe/hwpf/fapi/.empty b/src/ppe/hwpf/fapi/.empty new file mode 100755 index 0000000..e69de29 diff --git a/src/ppe/hwpf/fapi/docs/Doxyfile b/src/ppe/hwpf/fapi/docs/Doxyfile new file mode 100755 index 0000000..9cb5dc4 --- /dev/null +++ b/src/ppe/hwpf/fapi/docs/Doxyfile @@ -0,0 +1,2355 @@ +# Doxyfile 1.8.6 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a double hash (##) is considered a comment and is placed in +# front of the TAG it is preceding. +# +# All text after a single hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists, items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (\" \"). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all text +# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv +# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv +# for the list of possible encodings. +# The default value is: UTF-8. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by +# double-quotes, unless you are using Doxywizard) that should identify the +# project for which the documentation is generated. This name is used in the +# title of most generated pages and in a few other places. +# The default value is: My Project. + +PROJECT_NAME = "FAPI 2" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. This +# could be handy for archiving the generated documentation or if some version +# control system is used. + +PROJECT_NUMBER = + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer a +# quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = + +# With the PROJECT_LOGO tag one can specify an logo or icon that is included in +# the documentation. The maximum height of the logo should not exceed 55 pixels +# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo +# to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path +# into which the generated documentation will be written. If a relative path is +# entered, it will be relative to the location where doxygen was started. If +# left blank the current directory will be used. + +OUTPUT_DIRECTORY = genfiles + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub- +# directories (in 2 levels) under the output directory of each output format and +# will distribute the generated files over these directories. Enabling this +# option can be useful when feeding doxygen a huge amount of source files, where +# putting all generated files in the same directory would otherwise causes +# performance problems for the file system. +# The default value is: NO. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, +# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), +# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, +# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), +# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, +# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, +# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, +# Ukrainian and Vietnamese. +# The default value is: English. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member +# descriptions after the members that are listed in the file and class +# documentation (similar to Javadoc). Set to NO to disable this. +# The default value is: YES. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief +# description of a member or function before the detailed description +# +# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. +# The default value is: YES. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator that is +# used to form the text in various listings. Each string in this list, if found +# as the leading text of the brief description, will be stripped from the text +# and the result, after processing the whole list, is used as the annotated +# text. Otherwise, the brief description is used as-is. If left blank, the +# following values are used ($name is automatically replaced with the name of +# the entity):The $name class, The $name widget, The $name file, is, provides, +# specifies, contains, represents, a, an and the. + +ABBREVIATE_BRIEF = "The $name class" \ + "The $name widget" \ + "The $name file" \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# doxygen will generate a detailed section even if there is only a brief +# description. +# The default value is: NO. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. +# The default value is: NO. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path +# before files name in the file list and in the header files. If set to NO the +# shortest path that makes the file name unique will be used +# The default value is: YES. + +FULL_PATH_NAMES = YES + +# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path. +# Stripping is only done if one of the specified strings matches the left-hand +# part of the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the path to +# strip. +# +# Note that you can specify absolute paths here, but also relative paths, which +# will be relative from the directory where doxygen is started. +# This tag requires that the tag FULL_PATH_NAMES is set to YES. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the +# path mentioned in the documentation of a class, which tells the reader which +# header file to include in order to use a class. If left blank only the name of +# the header file containing the class definition is used. Otherwise one should +# specify the list of include paths that are normally passed to the compiler +# using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but +# less readable) file names. This can be useful is your file systems doesn't +# support long names like on DOS, Mac, or CD-ROM. +# The default value is: NO. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the +# first line (until the first dot) of a Javadoc-style comment as the brief +# description. If set to NO, the Javadoc-style will behave just like regular Qt- +# style comments (thus requiring an explicit @brief command for a brief +# description.) +# The default value is: NO. + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first +# line (until the first dot) of a Qt-style comment as the brief description. If +# set to NO, the Qt-style will behave just like regular Qt-style comments (thus +# requiring an explicit \brief command for a brief description.) +# The default value is: NO. + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a +# multi-line C++ special comment block (i.e. a block of //! or /// comments) as +# a brief description. This used to be the default behavior. The new default is +# to treat a multi-line C++ comment block as a detailed description. Set this +# tag to YES if you prefer the old behavior instead. +# +# Note that setting this tag to YES also means that rational rose comments are +# not recognized any more. +# The default value is: NO. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the +# documentation from any documented member that it re-implements. +# The default value is: YES. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a +# new page for each member. If set to NO, the documentation of a member will be +# part of the file/class/namespace that contains it. +# The default value is: NO. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen +# uses this value to replace tabs by spaces in code fragments. +# Minimum value: 1, maximum value: 16, default value: 4. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that act as commands in +# the documentation. An alias has the form: +# name=value +# For example adding +# "sideeffect=@par Side Effects:\n" +# will allow you to put the command \sideeffect (or @sideeffect) in the +# documentation, which will result in a user-defined paragraph with heading +# "Side Effects:". You can put \n's in the value part of an alias to insert +# newlines. + +ALIASES = + +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding "class=itcl::class" +# will allow you to use the command class in the itcl::class meaning. + +TCL_SUBST = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. For +# instance, some of the names that are used will be different. The list of all +# members will be omitted, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or +# Python sources only. Doxygen will then generate output that is more tailored +# for that language. For instance, namespaces will be presented as packages, +# qualified scopes will look different, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources. Doxygen will then generate output that is tailored for Fortran. +# The default value is: NO. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for VHDL. +# The default value is: NO. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, and +# language is one of the parsers supported by doxygen: IDL, Java, Javascript, +# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make +# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C +# (default is Fortran), use: inc=Fortran f=C. +# +# Note For files without extension you can use no_extension as a placeholder. +# +# Note that for custom extensions you also need to set FILE_PATTERNS otherwise +# the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments +# according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you can +# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in +# case of backward compatibilities issues. +# The default value is: YES. + +MARKDOWN_SUPPORT = NO + +# When enabled doxygen tries to link words that correspond to documented +# classes, or namespaces to their corresponding documentation. Such a link can +# be prevented in individual cases by by putting a % sign in front of the word +# or globally by setting AUTOLINK_SUPPORT to NO. +# The default value is: YES. + +AUTOLINK_SUPPORT = YES + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should set this +# tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); +# versus func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. +# The default value is: NO. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. +# The default value is: NO. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip (see: +# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen +# will parse them like normal C++ but will assume all classes use public instead +# of private inheritance when no explicit protection keyword is present. +# The default value is: NO. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. Setting this option to YES will make +# doxygen to replace the get and set methods by a property in the documentation. +# This will only work if the methods are indeed getting or setting a simple +# type. If this is not the case, or you want to show the methods anyway, you +# should set this option to NO. +# The default value is: YES. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. +# The default value is: NO. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES to allow class member groups of the same type +# (for instance a group of public functions) to be put as a subgroup of that +# type (e.g. under the Public Functions section). Set it to NO to prevent +# subgrouping. Alternatively, this can be done per class using the +# \nosubgrouping command. +# The default value is: YES. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions +# are shown inside the group in which they are included (e.g. using \ingroup) +# instead of on a separate page (for HTML and Man pages) or section (for LaTeX +# and RTF). +# +# Note that this feature does not work in combination with +# SEPARATE_MEMBER_PAGES. +# The default value is: NO. + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions +# with only public data fields or simple typedef fields will be shown inline in +# the documentation of the scope in which they are defined (i.e. file, +# namespace, or group documentation), provided this scope is documented. If set +# to NO, structs, classes, and unions are shown on a separate page (for HTML and +# Man pages) or section (for LaTeX and RTF). +# The default value is: NO. + +INLINE_SIMPLE_STRUCTS = NO + +# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or +# enum is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically be +# useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. +# The default value is: NO. + +TYPEDEF_HIDES_STRUCT = NO + +# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This +# cache is used to resolve symbols given their name and scope. Since this can be +# an expensive process and often the same symbol appears multiple times in the +# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small +# doxygen will become slower. If the cache is too large, memory is wasted. The +# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range +# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 +# symbols. At the end of a run doxygen will report the cache usage and suggest +# the optimal cache size from a speed point of view. +# Minimum value: 0, maximum value: 9, default value: 0. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. Private +# class members and static file members will be hidden unless the +# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. +# Note: This will also disable the warnings about undocumented members that are +# normally produced when WARNINGS is set to YES. +# The default value is: NO. + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will +# be included in the documentation. +# The default value is: NO. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal +# scope will be included in the documentation. +# The default value is: NO. + +EXTRACT_PACKAGE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file will be +# included in the documentation. +# The default value is: NO. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined +# locally in source files will be included in the documentation. If set to NO +# only classes defined in header files are included. Does not have any effect +# for Java sources. +# The default value is: YES. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local methods, +# which are defined in the implementation section but not in the interface are +# included in the documentation. If set to NO only methods in the interface are +# included. +# The default value is: NO. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base name of +# the file that contains the anonymous namespace. By default anonymous namespace +# are hidden. +# The default value is: NO. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all +# undocumented members inside documented classes or files. If set to NO these +# members will be included in the various overviews, but no documentation +# section is generated. This option has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. If set +# to NO these classes will be included in the various overviews. This option has +# no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend +# (class|struct|union) declarations. If set to NO these declarations will be +# included in the documentation. +# The default value is: NO. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any +# documentation blocks found inside the body of a function. If set to NO these +# blocks will be appended to the function's detailed documentation block. +# The default value is: NO. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation that is typed after a +# \internal command is included. If the tag is set to NO then the documentation +# will be excluded. Set it to YES to include the internal documentation. +# The default value is: NO. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file +# names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. +# The default value is: system dependent. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with +# their full class and namespace scopes in the documentation. If set to YES the +# scope will be hidden. +# The default value is: NO. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of +# the files that are included by a file in the documentation of that file. +# The default value is: YES. + +SHOW_INCLUDE_FILES = YES + +# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each +# grouped member an include statement to the documentation, telling the reader +# which file to include in order to use the member. +# The default value is: NO. + +SHOW_GROUPED_MEMB_INC = NO + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include +# files with double quotes in the documentation rather than with sharp brackets. +# The default value is: NO. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the +# documentation for inline members. +# The default value is: YES. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the +# (detailed) documentation of file and class members alphabetically by member +# name. If set to NO the members will appear in declaration order. +# The default value is: YES. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief +# descriptions of file, namespace and class members alphabetically by member +# name. If set to NO the members will appear in declaration order. Note that +# this will also influence the order of the classes in the class list. +# The default value is: NO. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the +# (brief and detailed) documentation of class members so that constructors and +# destructors are listed first. If set to NO the constructors will appear in the +# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. +# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief +# member documentation. +# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting +# detailed member documentation. +# The default value is: NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy +# of group names into alphabetical order. If set to NO the group names will +# appear in their defined order. +# The default value is: NO. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by +# fully-qualified names, including namespaces. If set to NO, the class list will +# be sorted only by class name, not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the alphabetical +# list. +# The default value is: NO. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper +# type resolution of all parameters of a function it will reject a match between +# the prototype and the implementation of a member function even if there is +# only one candidate or it is obvious which candidate to choose by doing a +# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still +# accept a match between prototype and implementation in such cases. +# The default value is: NO. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the +# todo list. This list is created by putting \todo commands in the +# documentation. +# The default value is: YES. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the +# test list. This list is created by putting \test commands in the +# documentation. +# The default value is: YES. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug +# list. This list is created by putting \bug commands in the documentation. +# The default value is: YES. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO) +# the deprecated list. This list is created by putting \deprecated commands in +# the documentation. +# The default value is: YES. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional documentation +# sections, marked by \if ... \endif and \cond +# ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the +# initial value of a variable or macro / define can have for it to appear in the +# documentation. If the initializer consists of more lines than specified here +# it will be hidden. Use a value of 0 to hide initializers completely. The +# appearance of the value of individual variables and macros / defines can be +# controlled using \showinitializer or \hideinitializer command in the +# documentation regardless of this setting. +# Minimum value: 0, maximum value: 10000, default value: 30. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at +# the bottom of the documentation of classes and structs. If set to YES the list +# will mention the files that were used to generate the documentation. +# The default value is: YES. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This +# will remove the Files entry from the Quick Index and from the Folder Tree View +# (if specified). +# The default value is: YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces +# page. This will remove the Namespaces entry from the Quick Index and from the +# Folder Tree View (if specified). +# The default value is: YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command command input-file, where command is the value of the +# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided +# by doxygen. Whatever the program writes to standard output is used as the file +# version. For an example see the documentation. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. You can +# optionally specify a file name after the option, if omitted DoxygenLayout.xml +# will be used as the name of the layout file. +# +# Note that if you run doxygen from a directory containing a file called +# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE +# tag is left empty. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files containing +# the reference definitions. This must be a list of .bib files. The .bib +# extension is automatically appended if omitted. This requires the bibtex tool +# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. +# For LaTeX the style of the bibliography can be controlled using +# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the +# search path. Do not use file names with spaces, bibtex cannot handle them. See +# also \cite for info how to create references. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated to +# standard output by doxygen. If QUIET is set to YES this implies that the +# messages are off. +# The default value is: NO. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES +# this implies that the warnings are on. +# +# Tip: Turn warnings on while writing the documentation. +# The default value is: YES. + +WARNINGS = YES + +# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate +# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: YES. + +WARN_IF_UNDOCUMENTED = YES + +# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some parameters +# in a documented function, or documenting parameters that don't exist or using +# markup commands wrongly. +# The default value is: YES. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that +# are documented, but have no documentation for their parameters or return +# value. If set to NO doxygen will only warn about wrong or incomplete parameter +# documentation, but not about the absence of documentation. +# The default value is: NO. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that doxygen +# can produce. The string should contain the $file, $line, and $text tags, which +# will be replaced by the file and line number from which the warning originated +# and the warning text. Optionally the format may contain $version, which will +# be replaced by the version of the file (if it could be obtained via +# FILE_VERSION_FILTER) +# The default value is: $file:$line: $text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning and error +# messages should be written. If left blank the output is written to standard +# error (stderr). + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag is used to specify the files and/or directories that contain +# documented source files. You may enter file names like myfile.cpp or +# directories like /usr/src/myproject. Separate the files or directories with +# spaces. +# Note: If this tag is empty the current directory is searched. + +INPUT = ../include ./topics + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses +# libiconv (or the iconv built into libc) for the transcoding. See the libiconv +# documentation (see: http://www.gnu.org/software/libiconv) for the list of +# possible encodings. +# The default value is: UTF-8. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank the +# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii, +# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp, +# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown, +# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf, +# *.qsf, *.as and *.js. + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.idl \ + *.ddl \ + *.odl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.cs \ + *.d \ + *.php \ + *.php4 \ + *.php5 \ + *.phtml \ + *.inc \ + *.m \ + *.markdown \ + *.md \ + *.mm \ + *.dox \ + *.py \ + *.f90 \ + *.f \ + *.for \ + *.tcl \ + *.vhd \ + *.vhdl \ + *.ucf \ + *.qsf \ + *.as \ + *.js \ + *.H + +# The RECURSIVE tag can be used to specify whether or not subdirectories should +# be searched for input files as well. +# The default value is: NO. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. +# The default value is: NO. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories use the pattern */test/* + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or directories +# that contain example code fragments that are included (see the \include +# command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank all +# files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude commands +# irrespective of the value of the RECURSIVE tag. +# The default value is: NO. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or directories +# that contain images that are to be included in the documentation (see the +# \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command: +# +# +# +# where is the value of the INPUT_FILTER tag, and is the +# name of an input file. Doxygen will then use the output that the filter +# program writes to standard output. If FILTER_PATTERNS is specified, this tag +# will be ignored. +# +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: pattern=filter +# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how +# filters are used. If the FILTER_PATTERNS tag is empty or if none of the +# patterns match the file name, INPUT_FILTER is applied. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER ) will also be used to filter the input files that are used for +# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). +# The default value is: NO. + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and +# it is also possible to disable source filtering for a specific pattern using +# *.ext= (so without naming a filter). +# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want to reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = README.md + +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will be +# generated. Documented entities will be cross-referenced with these sources. +# +# Note: To get rid of all source code in the generated output, make sure that +# also VERBATIM_HEADERS is set to NO. +# The default value is: NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body of functions, +# classes and enums directly into the documentation. +# The default value is: NO. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any +# special comment blocks from generated source code fragments. Normal C, C++ and +# Fortran comments will always remain visible. +# The default value is: YES. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES then for each documented +# function all documented functions referencing it will be listed. +# The default value is: NO. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES then for each documented function +# all documented entities called/used by that function will be listed. +# The default value is: NO. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set +# to YES, then the hyperlinks from functions in REFERENCES_RELATION and +# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will +# link to the documentation. +# The default value is: YES. + +REFERENCES_LINK_SOURCE = YES + +# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the +# source code will show a tooltip with additional information such as prototype, +# brief description and links to the definition and documentation. Since this +# will make the HTML file larger and loading of large files a bit slower, you +# can opt to disable this feature. +# The default value is: YES. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +SOURCE_TOOLTIPS = YES + +# If the USE_HTAGS tag is set to YES then the references to source code will +# point to the HTML generated by the htags(1) tool instead of doxygen built-in +# source browser. The htags tool is part of GNU's global source tagging system +# (see http://www.gnu.org/software/global/global.html). You will need version +# 4.8.6 or higher. +# +# To use it do the following: +# - Install the latest version of global +# - Enable SOURCE_BROWSER and USE_HTAGS in the config file +# - Make sure the INPUT points to the root of the source tree +# - Run doxygen as normal +# +# Doxygen will invoke htags (and that will in turn invoke gtags), so these +# tools must be available from the command line (i.e. in the search path). +# +# The result: instead of the source browser generated by doxygen, the links to +# source code will now point to the output of htags. +# The default value is: NO. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a +# verbatim copy of the header file for each class for which an include is +# specified. Set to NO to disable this. +# See also: Section \class. +# The default value is: YES. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all +# compounds will be generated. Enable this if the project contains a lot of +# classes, structs, unions or interfaces. +# The default value is: YES. + +ALPHABETICAL_INDEX = YES + +# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in +# which the alphabetical index list will be split. +# Minimum value: 1, maximum value: 20, default value: 5. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all classes will +# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag +# can be used to specify a prefix (or a list of prefixes) that should be ignored +# while generating the index headers. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output +# The default value is: YES. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a +# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of +# it. +# The default directory is: html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each +# generated HTML page (for example: .htm, .php, .asp). +# The default value is: .html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a user-defined HTML header file for +# each generated HTML page. If the tag is left blank doxygen will generate a +# standard header. +# +# To get valid HTML the header file that includes any scripts and style sheets +# that doxygen needs, which is dependent on the configuration options used (e.g. +# the setting GENERATE_TREEVIEW). It is highly recommended to start with a +# default header using +# doxygen -w html new_header.html new_footer.html new_stylesheet.css +# YourConfigFile +# and then modify the file new_header.html. See also section "Doxygen usage" +# for information on how to generate the default header that doxygen normally +# uses. +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. For a description +# of the possible markers and block names see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each +# generated HTML page. If the tag is left blank doxygen will generate a standard +# footer. See HTML_HEADER for more information on how to generate a default +# footer and what special commands can be used inside the footer. See also +# section "Doxygen usage" for information on how to generate the default footer +# that doxygen normally uses. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style +# sheet that is used by each HTML page. It can be used to fine-tune the look of +# the HTML output. If left blank doxygen will generate a default style sheet. +# See also section "Doxygen usage" for information on how to generate the style +# sheet that doxygen normally uses. +# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as +# it is more robust and this tag (HTML_STYLESHEET) will in the future become +# obsolete. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user- +# defined cascading style sheet that is included after the standard style sheets +# created by doxygen. Using this option one can overrule certain style aspects. +# This is preferred over using HTML_STYLESHEET since it does not replace the +# standard style sheet and is therefor more robust against future updates. +# Doxygen will copy the style sheet file to the output directory. For an example +# see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that the +# files will be copied as-is; there are no commands or markers available. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen +# will adjust the colors in the stylesheet and background images according to +# this color. Hue is specified as an angle on a colorwheel, see +# http://en.wikipedia.org/wiki/Hue for more information. For instance the value +# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 +# purple, and 360 is red again. +# Minimum value: 0, maximum value: 359, default value: 220. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors +# in the HTML output. For a value of 0 the output will use grayscales only. A +# value of 255 will produce the most vivid colors. +# Minimum value: 0, maximum value: 255, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the +# luminance component of the colors in the HTML output. Values below 100 +# gradually make the output lighter, whereas values above 100 make the output +# darker. The value divided by 100 is the actual gamma applied, so 80 represents +# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not +# change the gamma. +# Minimum value: 40, maximum value: 240, default value: 80. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting this +# to NO can help when comparing the output of multiple runs. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_TIMESTAMP = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries +# shown in the various tree structured indices initially; the user can expand +# and collapse entries dynamically later on. Doxygen will expand the tree to +# such a level that at most the specified number of entries are visible (unless +# a fully collapsed tree already exceeds this amount). So setting the number of +# entries 1 will produce a full collapsed tree by default. 0 is a special value +# representing an infinite number of entries and will result in a full expanded +# tree by default. +# Minimum value: 0, maximum value: 9999, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files will be +# generated that can be used as input for Apple's Xcode 3 integrated development +# environment (see: http://developer.apple.com/tools/xcode/), introduced with +# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a +# Makefile in the HTML output directory. Running make will produce the docset in +# that directory and running make install will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at +# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_DOCSET = NO + +# This tag determines the name of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# The default value is: Doxygen generated docs. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# This tag specifies a string that should uniquely identify the documentation +# set bundle. This should be a reverse domain-name style string, e.g. +# com.mycompany.MyDocSet. Doxygen will append .docset to the name. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. +# The default value is: org.doxygen.Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. +# The default value is: Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three +# additional HTML index files: index.hhp, index.hhc, and index.hhk. The +# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop +# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on +# Windows. +# +# The HTML Help Workshop contains a compiler that can convert all HTML output +# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML +# files are now used as the Windows 98 help format, and will replace the old +# Windows help format (.hlp) on all Windows platforms in the future. Compressed +# HTML files also contain an index, a table of contents, and you can search for +# words in the documentation. The HTML workshop also contains a viewer for +# compressed HTML files. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_HTMLHELP = NO + +# The CHM_FILE tag can be used to specify the file name of the resulting .chm +# file. You can add a path in front of the file if the result should not be +# written to the html output directory. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_FILE = + +# The HHC_LOCATION tag can be used to specify the location (absolute path +# including file name) of the HTML help compiler ( hhc.exe). If non-empty +# doxygen will try to run the HTML help compiler on the generated index.hhp. +# The file has to be specified with full path. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +HHC_LOCATION = + +# The GENERATE_CHI flag controls if a separate .chi index file is generated ( +# YES) or that it should be included in the master .chm file ( NO). +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +GENERATE_CHI = NO + +# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc) +# and project file content. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_INDEX_ENCODING = + +# The BINARY_TOC flag controls whether a binary table of contents is generated ( +# YES) or a normal table of contents ( NO) in the .chm file. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members to +# the table of contents of the HTML help documentation and to the tree view. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that +# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help +# (.qch) of the generated HTML documentation. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify +# the file name of the resulting .qch file. The path specified is relative to +# the HTML output folder. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help +# Project output. For more information please see Qt Help Project / Namespace +# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt +# Help Project output. For more information please see Qt Help Project / Virtual +# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- +# folders). +# The default value is: doc. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_VIRTUAL_FOLDER = doc + +# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom +# filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's filter section matches. Qt Help Project / Filter Attributes (see: +# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_SECT_FILTER_ATTRS = + +# The QHG_LOCATION tag can be used to specify the location of Qt's +# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the +# generated .qhp file. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be +# generated, together with the HTML files, they form an Eclipse help plugin. To +# install this plugin and make it available under the help contents menu in +# Eclipse, the contents of the directory containing the HTML and XML files needs +# to be copied into the plugins directory of eclipse. The name of the directory +# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. +# After copying Eclipse needs to be restarted before the help appears. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the Eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have this +# name. Each documentation set should have its own identifier. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# If you want full control over the layout of the generated HTML pages it might +# be necessary to disable the index and replace it with your own. The +# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top +# of each HTML page. A value of NO enables the index and the value YES disables +# it. Since the tabs in the index contain the same information as the navigation +# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. If the tag +# value is set to YES, a side panel will be generated containing a tree-like +# index structure (just like the one that is generated for HTML Help). For this +# to work a browser that supports JavaScript, DHTML, CSS and frames is required +# (i.e. any modern browser). Windows users are probably better off using the +# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can +# further fine-tune the look of the index. As an example, the default style +# sheet generated by doxygen has an example that shows how to put an image at +# the root of the tree instead of the PROJECT_NAME. Since the tree basically has +# the same information as the tab index, you could consider setting +# DISABLE_INDEX to YES when enabling this option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_TREEVIEW = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that +# doxygen will group on one line in the generated HTML documentation. +# +# Note that a value of 0 will completely suppress the enum values from appearing +# in the overview section. +# Minimum value: 0, maximum value: 20, default value: 4. +# This tag requires that the tag GENERATE_HTML is set to YES. + +ENUM_VALUES_PER_LINE = 1 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used +# to set the initial width (in pixels) of the frame in which the tree is shown. +# Minimum value: 0, maximum value: 1500, default value: 250. +# This tag requires that the tag GENERATE_HTML is set to YES. + +TREEVIEW_WIDTH = 250 + +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to +# external symbols imported via tag files in a separate window. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of LaTeX formulas included as images in +# the HTML documentation. When you change the font size after a successful +# doxygen run you need to manually remove any form_*.png images from the HTML +# output directory to force them to be regenerated. +# Minimum value: 8, maximum value: 50, default value: 10. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are not +# supported properly for IE 6.0, but are supported on all modern browsers. +# +# Note that when changing this option you need to delete any form_*.png files in +# the HTML output directory before the changes have effect. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see +# http://www.mathjax.org) which uses client side Javascript for the rendering +# instead of using prerendered bitmaps. Use this if you do not have LaTeX +# installed or if you want to formulas look prettier in the HTML output. When +# enabled you may also need to install MathJax separately and configure the path +# to it using the MATHJAX_RELPATH option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. See the MathJax site (see: +# http://docs.mathjax.org/en/latest/output.html) for more details. +# Possible values are: HTML-CSS (which is slower, but has the best +# compatibility), NativeMML (i.e. MathML) and SVG. +# The default value is: HTML-CSS. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the HTML +# output directory using the MATHJAX_RELPATH option. The destination directory +# should contain the MathJax.js script. For instance, if the mathjax directory +# is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax +# Content Delivery Network so you can quickly see the result without installing +# MathJax. However, it is strongly recommended to install a local copy of +# MathJax from http://www.mathjax.org before deployment. +# The default value is: http://cdn.mathjax.org/mathjax/latest. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax +# extension names that should be enabled during MathJax rendering. For example +# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces +# of code that will be used on startup of the MathJax code. See the MathJax site +# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# example see the documentation. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for +# the HTML output. The underlying search engine uses javascript and DHTML and +# should work on any modern browser. Note that when using HTML help +# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) +# there is already a search function so this one should typically be disabled. +# For large projects the javascript based search engine can be slow, then +# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to +# search using the keyboard; to jump to the search box use + S +# (what the is depends on the OS and browser, but it is typically +# , /