From 1c880c957a74d066ae23bab4a52b63bcf5824293 Mon Sep 17 00:00:00 2001 From: Wael El-Essawy Date: Tue, 19 Jan 2016 13:22:06 -0600 Subject: Enable Master-slave OCC communication Change-Id: I445072e20d599e30f80cc8059b3f3b2a956c453e RTC: 133154 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22005 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles Reviewed-by: Christopher J. Cain Reviewed-by: William A. Bryan --- src/ssx/occhw/occhw.h | 14 ++++++++++++-- src/ssx/occhw/occhw_async.c | 5 ----- src/ssx/occhw/occhw_async.h | 6 +++--- src/ssx/occhw/occhw_async_pba.c | 6 +++--- src/ssx/occhw/occhw_init.c | 3 ++- src/ssx/occhw/occhw_pba.c | 12 ++++++------ src/ssx/ssx/ssx_api.h | 18 ++++++++++++++++++ src/ssx/trace/ssx_trace.h | 1 + src/ssx/trace/ssx_trace_core.c | 4 ++++ 9 files changed, 49 insertions(+), 20 deletions(-) (limited to 'src/ssx') diff --git a/src/ssx/occhw/occhw.h b/src/ssx/occhw/occhw.h index b0ddda8..c0f11df 100644 --- a/src/ssx/occhw/occhw.h +++ b/src/ssx/occhw/occhw.h @@ -327,8 +327,18 @@ extern Ppc405MmuMap G_applet1_mmu_map; #endif /* __ASSEMBLER__ */ -// OCCHW defines a private version of dcache_flush_all() that uses the undefined -// OCI space at 0x20000000; See dcache_flush_all() in occhw_cache.S. +// OCCHW defines a private version of dcache_flush_all() that uses undefined +// OCI space defined by OCCHW_FLUSH_ZERO_ADDRESS. +// See dcache_flush_all() in occhw_cache.S. +// +// DCCR bit | OCCHW_FLUSH_ZERO_ADDRESS ( see 405 spec for full table) +// ---------|------------------------------------------ +// 0 | 0x00000000 - 0x07ffffff +// 1 | 0x08000000 - 0x0fffffff +// 4 | 0x20000000 - 0x27ffffff +// 8 | 0x40000000 - 0x47ffffff (undefined range - use for dcache flush) +// 16 | 0x80000000 - 0x87ffffff (overlaps PBA defined space) +// 31 | 0xF8000000 - 0xffffffff (overlaps SRAM) #define USE_GENERIC_DCACHE_FLUSH_ALL 0 #define OCCHW_FLUSH_ZERO_ADDRESS 0x20000000 diff --git a/src/ssx/occhw/occhw_async.c b/src/ssx/occhw/occhw_async.c index f0fbbca..ae3273b 100644 --- a/src/ssx/occhw/occhw_async.c +++ b/src/ssx/occhw/occhw_async.c @@ -999,8 +999,6 @@ async_initialize() async_gpe_initialize(&G_async_gpe_queue3, ASYNC_ENGINE_GPE3); - // TODO: add these back in as they are ported to P9 -#if 0 // BCE async_bce_initialize(&G_pba_bcde_queue, @@ -1010,7 +1008,6 @@ async_initialize() async_bce_initialize(&G_pba_bcue_queue, ASYNC_ENGINE_BCUE, OCCHW_IRQ_PBA_BCUE_ATTN); -#endif // OCB @@ -1062,7 +1059,6 @@ async_initialize() OCB_WRITE3_LENGTH, OCB_WRITE3_PROTOCOL); -#if 0 // PBAX async_pbax_initialize(&G_pbax_read_queue[0], @@ -1078,5 +1074,4 @@ async_initialize() G_pbax_read1_buffer, PBAX_READ1_LENGTH, PBAX_READ1_PROTOCOL); -#endif } diff --git a/src/ssx/occhw/occhw_async.h b/src/ssx/occhw/occhw_async.h index e2bbf0a..be2996f 100644 --- a/src/ssx/occhw/occhw_async.h +++ b/src/ssx/occhw/occhw_async.h @@ -641,13 +641,13 @@ typedef struct { pba_fir_t fir; /// PBA Error Report 0 - pba_errpt0_t errpt0; + pba_errrpt0_t errrpt0; /// PBA Error Report 1 - pba_errpt1_t errpt1; + pba_errrpt1_t errrpt1; /// PBA Error Report 2 - pba_errpt2_t errpt2; + pba_errrpt2_t errrpt2; /// PBA Read Buffer Valid Status pba_rbufvaln_t rbufval[PBA_READ_BUFFERS]; diff --git a/src/ssx/occhw/occhw_async_pba.c b/src/ssx/occhw/occhw_async_pba.c index 3a03a17..b4bc8fb 100644 --- a/src/ssx/occhw/occhw_async_pba.c +++ b/src/ssx/occhw/occhw_async_pba.c @@ -140,9 +140,9 @@ pba_common_ffdc(PbaCommonFfdc* ffdc) } getscom(PBA_FIR, &(ffdc->fir.value)); - getscom(PBA_ERRPT0, &(ffdc->errpt0.value)); - getscom(PBA_ERRPT1, &(ffdc->errpt1.value)); - getscom(PBA_ERRPT2, &(ffdc->errpt2.value)); + getscom(PBA_ERRRPT0, &(ffdc->errrpt0.value)); + getscom(PBA_ERRRPT1, &(ffdc->errrpt1.value)); + getscom(PBA_ERRRPT2, &(ffdc->errrpt2.value)); ffdc->error = 1; } diff --git a/src/ssx/occhw/occhw_init.c b/src/ssx/occhw/occhw_init.c index f3383b4..bbb67bd 100644 --- a/src/ssx/occhw/occhw_init.c +++ b/src/ssx/occhw/occhw_init.c @@ -174,6 +174,7 @@ static const MmuRegion mmu_regions[] = { 0, DATA_CACHEABILITY_FLAG | TEXT_CACHEABILITY_FLAG | TLBLO_EX | TLBLO_WR, &G_ex_free_mmu_map}, +/* {(SsxAddress)&_APPLET0_SECTION_BASE, (size_t)&_APPLET0_SECTION_SIZE, 0, DATA_CACHEABILITY_FLAG | TEXT_CACHEABILITY_FLAG | TLBLO_WR | TLBLO_EX, @@ -183,7 +184,7 @@ static const MmuRegion mmu_regions[] = { (size_t)&_APPLET1_SECTION_SIZE, 0, DATA_CACHEABILITY_FLAG | TEXT_CACHEABILITY_FLAG | TLBLO_WR | TLBLO_EX, &G_applet1_mmu_map}, - +*/ {(SsxAddress)OCI_REGISTER_SPACE_BASE, (size_t)OCI_REGISTER_SPACE_SIZE, 0, TLBLO_WR | TLBLO_I | TLBLO_G, 0} , diff --git a/src/ssx/occhw/occhw_pba.c b/src/ssx/occhw/occhw_pba.c index 4c21bb8..5ba18d5 100644 --- a/src/ssx/occhw/occhw_pba.c +++ b/src/ssx/occhw/occhw_pba.c @@ -257,13 +257,13 @@ pba_slave_reset(int id) /// not valid for some reason. int -pbax_configure(int master, int node, int chip, int group_mask) +pbax_configure(int master, int group, int chip, int group_mask) { pba_xcfg_t pxc; if (SSX_ERROR_CHECK_API) { - SSX_ERROR_IF((node < 0) || - (node >= PBAX_NODES) || + SSX_ERROR_IF((group < 0) || + (group >= PBAX_GROUPS) || (chip < 0) || (chip >= PBAX_CHIPS) || (group_mask < 0) || @@ -272,7 +272,7 @@ pbax_configure(int master, int node, int chip, int group_mask) } pxc.value = in64(PBA_XCFG); pxc.fields.reservation_en = (master != 0); - pxc.fields.rcv_nodeid = node; + pxc.fields.rcv_groupid = group; pxc.fields.rcv_chipid = chip; pxc.fields.rcv_brdcst_group = group_mask; out64(PBA_XCFG, pxc.value); @@ -312,7 +312,7 @@ pbax_configure(int master, int node, int chip, int group_mask) int pbax_target_create(PbaxTarget* target, int type, int scope, int queue, - int node, int chip_or_group) + int group, int chip_or_group) { if (SSX_ERROR_CHECK_API) { SSX_ERROR_IF(target == 0, PBAX_INVALID_OBJECT); @@ -327,7 +327,7 @@ pbax_target_create(PbaxTarget* target, target->target.fields.snd_qid = queue; target->target.fields.snd_type = type; target->target.fields.snd_reservation = (type == PBAX_BROADCAST); - target->target.fields.snd_nodeid = node; + target->target.fields.snd_groupid = group; target->target.fields.snd_chipid = chip_or_group; return 0; diff --git a/src/ssx/ssx/ssx_api.h b/src/ssx/ssx/ssx_api.h index e4f6a10..bcdd0fb 100644 --- a/src/ssx/ssx/ssx_api.h +++ b/src/ssx/ssx/ssx_api.h @@ -538,6 +538,24 @@ typedef struct { #define SSXTRACE_BIN(str, bufp, buf_size) #endif //SSX_TRACE_SUPPORT +//Needed for easy cache flush of trace buffer +//Note, in order to use this macro you must declare g_ssx_trace_buf[_size] +// as extern SsxTraceBuffer [and size_t] variables in the .c file as well +// as include ssx_trace.h. +#if (SSX_TRACE_ENABLE && SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT) +#define SSX_FLUSH_TRACE_BUF() dcache_flush(&g_ssx_trace_buf, g_ssx_trace_buf_size) +#else +#define SSX_FLUSH_TRACE_BUF() +#endif + +//Making sure we can still compile application codes if SSX tracing for some +// reason isn't enabled. +#if (SSX_TRACE_ENABLE && SSX_TRACE_SUPPORT && SSX_TIMER_SUPPORT) +#define SSX_TRACE_INIT(freqhz, time0) ssx_trace_init(freqhz, time0) +#else +#define SSX_TRACE_INIT(freqhz, time0) +#endif + /// A generic doubly-linked list object /// /// This object functions both as a sentinel mode for a deque as well as a diff --git a/src/ssx/trace/ssx_trace.h b/src/ssx/trace/ssx_trace.h index c79452b..3f4505f 100644 --- a/src/ssx/trace/ssx_trace.h +++ b/src/ssx/trace/ssx_trace.h @@ -299,5 +299,6 @@ typedef struct }SsxTraceBuffer; extern SsxTraceBuffer g_ssx_trace_buf; +extern size_t g_ssx_trace_buf_size; #endif /* __SSX_TRACE_H__ */ diff --git a/src/ssx/trace/ssx_trace_core.c b/src/ssx/trace/ssx_trace_core.c index a2db4b8..de9d309 100644 --- a/src/ssx/trace/ssx_trace_core.c +++ b/src/ssx/trace/ssx_trace_core.c @@ -162,4 +162,8 @@ void ssx_trace_init(uint32_t timebase_frequency_hz, 0); } +////Needed for easy cache flush of trace buffer +size_t g_ssx_trace_buf_size=sizeof(g_ssx_trace_buf); + + #endif -- cgit v1.2.1