From d85d3c5387ec9829ef29b98c16112210f343bae7 Mon Sep 17 00:00:00 2001 From: Zane Shelley Date: Thu, 6 Dec 2018 11:17:18 -0600 Subject: FIRDATA: add Axone memory subsystem SCOM support Change-Id: Iaa32e0cc115f5c72e2b8e19f55e3148d115b5aa8 RTC: 201994 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69530 Tested-by: FSP CI Jenkins Reviewed-by: Caleb N. Palmer Reviewed-by: Brian J. Stegmiller Reviewed-by: Martha Broyles --- src/occ_gpe0/firdata/scom_util.c | 59 ++++++++++++++++++++++++++++++++++++++-- src/occ_gpe0/firdata/scom_util.h | 20 ++++++++++++-- 2 files changed, 75 insertions(+), 4 deletions(-) (limited to 'src/occ_gpe0') diff --git a/src/occ_gpe0/firdata/scom_util.c b/src/occ_gpe0/firdata/scom_util.c index 2b328b0..fd4dfee 100644 --- a/src/occ_gpe0/firdata/scom_util.c +++ b/src/occ_gpe0/firdata/scom_util.c @@ -200,13 +200,13 @@ int32_t translate_addr( SCOM_Trgt_t i_trgt, uint64_t i_addr, uint64_t * o_addr ) set_chiplet_id(EC00_CHIPLET_ID + l_chip_unit_num, o_addr); } else if(i_trgt.type == TRGT_MCS || //MCS - i_trgt.type == TRGT_MI) //MI TODO RTC 175488 + i_trgt.type == TRGT_MI) //MI { set_chiplet_id(N3_CHIPLET_ID - (2 * (l_chip_unit_num / 2)), o_addr); set_sat_id(2 * (l_chip_unit_num % 2), o_addr); } else if(i_trgt.type == TRGT_MCBIST || //MCBIST - i_trgt.type == TRGT_MC) //MC TODO RTC 175488 + i_trgt.type == TRGT_MC) //MC { set_chiplet_id(MC01_CHIPLET_ID + l_chip_unit_num, o_addr); } @@ -242,6 +242,61 @@ int32_t translate_addr( SCOM_Trgt_t i_trgt, uint64_t i_addr, uint64_t * o_addr ) set_sat_offset(l_mcs_sat_offset, o_addr); } } + else if ( i_trgt.type == TRGT_MCC ) + { + if (((get_chiplet_id(i_addr) == N3_CHIPLET_ID) || (get_chiplet_id(i_addr) == N1_CHIPLET_ID))) + { + //SCOM3 (See mc_clscom_rlm.fig <= 0xB vs mc_scomfir_rlm.fig > 0xB) + //DMI0 05 02 0 0x2X (X <= 0xB) + //DMI1 05 02 0 0x3X (X <= 0xB) + //DMI2 05 02 2 0x2X (X <= 0xB) + //DMI3 05 02 2 0x3X (X <= 0xB) + //DMI4 03 02 0 0x2X (X <= 0xB) + //DMI5 03 02 0 0x3X (X <= 0xB) + //DMI6 03 02 2 0x2X (X <= 0xB) + //DMI7 03 02 2 0x3X (X <= 0xB) + set_chiplet_id(N3_CHIPLET_ID - (2 * (l_chip_unit_num / 4)), o_addr); + set_sat_id(2 * ((l_chip_unit_num / 2) % 2), o_addr); + uint8_t l_sat_offset = get_sat_offset(i_addr); + l_sat_offset = (l_sat_offset & 0xF) + ((2 + (l_chip_unit_num % 2)) << 4); + set_sat_offset(l_sat_offset, o_addr); + } + + if (((get_chiplet_id(i_addr) == MC01_CHIPLET_ID) || (get_chiplet_id(i_addr) == MC23_CHIPLET_ID))) + { + //CHANX.USTL. Sat_id: 10 + port_id (8,9,10,11) + //CHANX.DSTL. Sat_id: 01 + port_id (4,5,6,7) + set_chiplet_id(MC01_CHIPLET_ID + (l_chip_unit_num / 4), o_addr); + + uint8_t l_sat_id = get_sat_id(i_addr); + + if (P9A_MC_DSTL_CHAN0_SAT_ID <= l_sat_id && l_sat_id <= P9A_MC_DSTL_CHAN3_SAT_ID) + { + set_sat_id(P9A_MC_DSTL_CHAN0_SAT_ID + (l_chip_unit_num % 4), o_addr); + } + + if (P9A_MC_USTL_CHAN0_SAT_ID <= l_sat_id && l_sat_id <= P9A_MC_USTL_CHAN3_SAT_ID) + { + set_sat_id(P9A_MC_USTL_CHAN0_SAT_ID + (l_chip_unit_num % 4), o_addr); + } + } + } + else if ( i_trgt.type == TRGT_OMIC ) + { + set_chiplet_id(MC01_CHIPLET_ID + (l_chip_unit_num / 3), o_addr); + + uint8_t l_ring_id = get_ring(i_addr) & 0xF; + + if (P9A_MC_OMIC0_RING_ID <= l_ring_id && l_ring_id <= P9A_MC_OMIC2_RING_ID) + { + set_ring(P9A_MC_OMIC0_RING_ID + (l_chip_unit_num % 3), o_addr); + } + + if (P9A_MC_OMIC0_PPE_RING_ID <= l_ring_id && l_ring_id <= P9A_MC_OMIC2_PPE_RING_ID) + { + set_ring(P9A_MC_OMIC0_PPE_RING_ID + (l_chip_unit_num % 3), o_addr); + } + } else { TRAC_ERR( FUNC"unsupported unit type %d", i_trgt.type ); diff --git a/src/occ_gpe0/firdata/scom_util.h b/src/occ_gpe0/firdata/scom_util.h index 1ec7fd2..278f304 100644 --- a/src/occ_gpe0/firdata/scom_util.h +++ b/src/occ_gpe0/firdata/scom_util.h @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/occ_405/firdata/scom_util.h $ */ +/* $Source: src/occ_gpe0/firdata/scom_util.h $ */ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -73,6 +73,22 @@ typedef enum N2_PCIS0_0_RING_ID = 0x3, ///< PCIS0_0 } p9_n2_ring_id_t; +typedef enum +{ + P9A_MC_OMIC0_RING_ID = 0x4, ///< OMIC0 + P9A_MC_OMIC2_RING_ID = 0x6, ///< OMIC2 + P9A_MC_OMIC0_PPE_RING_ID = 0x9, ///< OMIC0 PPE + P9A_MC_OMIC2_PPE_RING_ID = 0xB, ///< OMIC2 PPE +} p9a_mc_ring_id_t; + +typedef enum +{ + P9A_MC_DSTL_CHAN0_SAT_ID = 0x4, ///< DSTL registers channel 0 + P9A_MC_DSTL_CHAN3_SAT_ID = 0x7, ///< DSTL registers channel 3 + P9A_MC_USTL_CHAN0_SAT_ID = 0x8, ///< USTL registers channel 0 + P9A_MC_USTL_CHAN3_SAT_ID = 0xB, ///< USTL registers channel 3 +} p9a_mc_sat_id_t; + /** @brief Performs a hardware scom on a regular register. * @param i_trgt The SCOM target. * @param i_addr 32-bit SCOM address. -- cgit v1.2.1