From 3d71bd95e10f82ae2a96e6ebc929dc2ca7b1b63c Mon Sep 17 00:00:00 2001 From: mbroyles Date: Tue, 18 Jul 2017 16:32:36 -0500 Subject: Fix IPS enter/exit time happening in half the time it should be Change-Id: Ibae3b77afbb42a34efe622c5da3aba391ee92bae Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43288 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan Reviewed-by: Christopher J. Cain Reviewed-by: Martha Broyles --- src/occ_405/amec/amec_master_smh.c | 240 ++++++++----------------------------- src/occ_405/amec/amec_master_smh.h | 41 +------ src/occ_405/occ_sys_config.h | 7 +- src/occ_405/rtls/rtls.h | 10 ++ 4 files changed, 63 insertions(+), 235 deletions(-) (limited to 'src/occ_405') diff --git a/src/occ_405/amec/amec_master_smh.c b/src/occ_405/amec/amec_master_smh.c index 9fce8ef..0fcee20 100755 --- a/src/occ_405/amec/amec_master_smh.c +++ b/src/occ_405/amec/amec_master_smh.c @@ -52,10 +52,10 @@ // Defines/Enums //*************************************************************************/ -//Power cap mismatch threshold set to 8 ticks (2 milliseconds) +//Power cap mismatch threshold set to 8 ticks #define PCAPS_MISMATCH_THRESHOLD 8 -//Power cap failure threshold set to 32 (ticks) +//Power cap failure threshold set to 32 ticks #define PCAP_FAILURE_THRESHOLD 32 //*************************************************************************/ @@ -91,98 +91,36 @@ uint16_t G_mst_soft_fmax = 0xFFFF; uint8_t G_mst_violation_cnt[MAX_OCCS] = {0}; // -------------------------------------------------------- -// AMEC Master State 6.1 Substate Table +// AMEC Master State 5 Substate Table // -------------------------------------------------------- -// Each function inside this state table runs once every 128ms. +// Each substate runs every 64th tick time = 64 * MICS_PER_TICK // -const smh_tbl_t amec_mst_state_6_1_sub_substate_table[AMEC_SMH_STATES_PER_LVL] = +const smh_tbl_t amec_mst_state_5_substate_table[AMEC_SMH_STATES_PER_LVL] = { - {amec_mst_sub_substate_6_1_0, NULL}, - {amec_mst_sub_substate_6_1_1, NULL}, - {amec_mst_sub_substate_6_1_2, NULL}, - {amec_mst_sub_substate_6_1_3, NULL}, - {amec_mst_sub_substate_6_1_4, NULL}, - {amec_mst_sub_substate_6_1_5, NULL}, - {amec_mst_sub_substate_6_1_6, NULL}, - {amec_mst_sub_substate_6_1_7, NULL}, -}; - -// -------------------------------------------------------- -// AMEC Master State 0 Substate Table -// -------------------------------------------------------- -// Each function inside this state table runs once every 16ms. -// -// The 2 States are interleaved so each one runs every 4ms. -// -const smh_tbl_t amec_mst_state_0_substate_table[AMEC_SMH_STATES_PER_LVL] = -{ - {amec_mst_substate_0_0, NULL}, - {amec_mst_substate_0_1, NULL}, - {amec_mst_substate_0_0, NULL}, - {amec_mst_substate_0_1, NULL}, - {amec_mst_substate_0_0, NULL}, - {amec_mst_substate_0_1, NULL}, - {amec_mst_substate_0_0, NULL}, - {amec_mst_substate_0_1, NULL}, -}; - -// -------------------------------------------------------- -// AMEC Master State 3 Substate Table -// -------------------------------------------------------- -// Each function inside this state table runs once every 16ms. -// -// The 2 States are interleaved so each one runs every 4ms. -// -const smh_tbl_t amec_mst_state_3_substate_table[AMEC_SMH_STATES_PER_LVL] = - -{ - {amec_mst_substate_3_0, NULL}, - {amec_mst_substate_3_1, NULL}, - {amec_mst_substate_3_0, NULL}, - {amec_mst_substate_3_1, NULL}, - {amec_mst_substate_3_0, NULL}, - {amec_mst_substate_3_1, NULL}, - {amec_mst_substate_3_0, NULL}, - {amec_mst_substate_3_1, NULL}, -}; - -// -------------------------------------------------------- -// AMEC Master State 6 Substate Table -// -------------------------------------------------------- -// Each function inside this state table runs once every 16ms. -// -// SubState1: 8 Sub-substates (128ms/sub-substate) -// -const smh_tbl_t amec_mst_state_6_substate_table[AMEC_SMH_STATES_PER_LVL] = -{ - {amec_mst_substate_6_0, NULL}, - {amec_mst_substate_6_1, amec_mst_state_6_1_sub_substate_table}, - {amec_mst_substate_6_2, NULL}, - {amec_mst_substate_6_3, NULL}, - {amec_mst_substate_6_4, NULL}, - {amec_mst_substate_6_5, NULL}, - {amec_mst_substate_6_6, NULL}, - {amec_mst_substate_6_7, NULL}, + {amec_mst_substate_5_even, NULL}, // Substate 5.0 + {NULL, NULL}, // Substate 5.1 (not used) + {amec_mst_substate_5_even, NULL}, // Substate 5.2 + {NULL, NULL}, // Substate 5.3 (not used) + {amec_mst_substate_5_even, NULL}, // Substate 5.4 + {NULL, NULL}, // Substate 5.5 (not used) + {amec_mst_substate_5_even, NULL}, // Substate 5.6 + {NULL, NULL}, // Substate 5.7 (not used) }; // -------------------------------------------------------- // Main AMEC Master State Table // -------------------------------------------------------- -// Each function inside this state table runs once every 2ms. -// -// State0: 2 Substates (4ms/substate) -// State3: 2 Substates (4ms/substate) -// State6: 8 Substates (16ms/substate) +// Each function inside this state table runs once every MICS_PER_TICK * 8 // const smh_tbl_t amec_mst_state_table[AMEC_SMH_STATES_PER_LVL] = { - {amec_mst_state_0, amec_mst_state_0_substate_table}, + {amec_mst_state_0, NULL}, {amec_mst_state_1, NULL}, {amec_mst_state_2, NULL}, - {amec_mst_state_3, amec_mst_state_3_substate_table}, + {amec_mst_state_3, NULL}, {amec_mst_state_4, NULL}, - {amec_mst_state_5, NULL}, - {amec_mst_state_6, amec_mst_state_6_substate_table}, + {amec_mst_state_5, amec_mst_state_5_substate_table}, + {amec_mst_state_6, NULL}, {amec_mst_state_7, NULL}, }; @@ -378,8 +316,7 @@ void amec_mst_check_pcaps_match(void) G_pcaps_mismatch_count, l_prev_pcap, l_chip_id, G_slave_active_pcaps[l_chip_id].active_pcap, G_slave_active_pcaps[l_chip_id].pcap_valid); - //If mismatch occurs for 8 consecutive ticks - //i.e 8 * 250 microsecs = 2 milliseconds,then reset occ + //If mismatch occurs for 8 consecutive ticks then reset occ if(G_pcaps_mismatch_count >= PCAPS_MISMATCH_THRESHOLD) { TRAC_ERR("Mismatch in OCC power cap values: pcap=%d, slave_active_pcap[%d]=%d(%d)", @@ -936,33 +873,7 @@ void amec_mst_state_1(void){AMEC_DBG("\tAMEC Master State 1\n");} void amec_mst_state_2(void){AMEC_DBG("\tAMEC Master State 2\n");} void amec_mst_state_3(void){AMEC_DBG("\tAMEC Master State 3\n");} void amec_mst_state_4(void){AMEC_DBG("\tAMEC Master State 4\n");} - -void amec_mst_state_5(void) -{ - /*------------------------------------------------------------------------*/ - /* Local Variables */ - /*------------------------------------------------------------------------*/ - static uint16_t l_counter = 0; - - /*------------------------------------------------------------------------*/ - /* Code */ - /*------------------------------------------------------------------------*/ - AMEC_DBG("\tAMEC Master State 5\n"); - - // Only execute if OCC is in the active state - if ( IS_OCC_STATE_ACTIVE() ) - { - // Increment our local counter - l_counter++; - - // Is it time to run the Idle Power Saver algorithm? (default is 3sec) - if (l_counter == AMEC_DPS_SAMPLING_RATE * AMEC_IPS_AVRG_INTERVAL) - { - l_counter = 0; - amec_mst_ips_main(); - } - } -} +void amec_mst_state_5(void){AMEC_DBG("\tAMEC Master State 5\n");} void amec_mst_state_6(void) { @@ -985,94 +896,43 @@ void amec_mst_state_7(void){AMEC_DBG("\tAMEC Master State 7\n");} // Function Specification // -// Name: amec_mst_substate_0_0 -// amec_mst_substate_0_1 +// Name: amec_mst_substate_5_even // -// Description: master substate amec_mst_substate_0_0 -// master substate amec_mst_substate_0_1 +// Description: state 5 even numbered master substates for IPS +// gives state 5 substate function to be called every 16th tick +// This must be called at the same frequency as CORE_DATA_COLLECTION_US +// for IPS enter/exit timings to work correctly +// Time = MICS_PER_TICK * MAX_NUM_TICKS +// odd substates of state 5 are not currently used // // End Function Specification -void amec_mst_substate_0_0(void){AMEC_DBG("\tAMEC Master SubState 0.0\n");} -void amec_mst_substate_0_1(void){AMEC_DBG("\tAMEC Master SubState 0.1\n");} +void amec_mst_substate_5_even(void) +{ + /*------------------------------------------------------------------------*/ + /* Local Variables */ + /*------------------------------------------------------------------------*/ + static uint16_t l_counter = 0; -// Function Specification -// -// Name: amec_mst_substate_6_0 -// amec_mst_substate_6_1 -// amec_mst_substate_6_2 -// amec_mst_substate_6_3 -// amec_mst_substate_6_4 -// amec_mst_substate_6_5 -// amec_mst_substate_6_6 -// amec_mst_substate_6_7 -// -// Description: master substate amec_mst_substate_6_0 -// master substate amec_mst_substate_6_1 -// master substate amec_mst_substate_6_2 -// master substate amec_mst_substate_6_3 -// master substate amec_mst_substate_6_4 -// master substate amec_mst_substate_6_5 -// master substate amec_mst_substate_6_6 -// master substate amec_mst_substate_6_7 -// -// Flow: FN= None -// -// End Function Specification -void amec_mst_substate_6_0(void){AMEC_DBG("\tAMEC Master State 6.0\n");} -void amec_mst_substate_6_1(void){AMEC_DBG("\tAMEC Master State 6.1\n");} -void amec_mst_substate_6_2(void){AMEC_DBG("\tAMEC Master State 6.2\n");} -void amec_mst_substate_6_3(void){AMEC_DBG("\tAMEC Master State 6.3\n");} -void amec_mst_substate_6_4(void){AMEC_DBG("\tAMEC Master State 6.4\n");} -void amec_mst_substate_6_5(void){AMEC_DBG("\tAMEC Master State 6.5\n");} -void amec_mst_substate_6_6(void){AMEC_DBG("\tAMEC Master State 6.6\n");} -void amec_mst_substate_6_7(void){AMEC_DBG("\tAMEC Master State 6.7\n");} + /*------------------------------------------------------------------------*/ + /* Code */ + /*------------------------------------------------------------------------*/ + AMEC_DBG("\tAMEC Master State 5 even substate\n"); -// Function Specification -// -// Name: amec_mst_substate_3_0 -// amec_mst_substate_3_1 -// -// Description: master substate amec_mst_substate_3_0 -// master substate amec_mst_substate_3_1 -// -// Flow: FN= None -// -// End Function Specification -void amec_mst_substate_3_0(void){AMEC_DBG("\tAMEC Master State 3.0\n");} -void amec_mst_substate_3_1(void){AMEC_DBG("\tAMEC Master State 3.1\n");} + // Only execute if OCC is in the active state + if ( IS_OCC_STATE_ACTIVE() ) + { + // Increment our local counter + l_counter++; + // Is it time to run the Idle Power Saver algorithm? (default is 3sec) + if (l_counter == AMEC_DPS_SAMPLING_RATE * AMEC_IPS_AVRG_INTERVAL) + { + l_counter = 0; + amec_mst_ips_main(); + } + } +} -// Function Specification -// -// Name: amec_mst_substate_6_1_0 -// amec_mst_substate_6_1_1 -// amec_mst_substate_6_1_2 -// amec_mst_substate_6_1_3 -// amec_mst_substate_6_1_4 -// amec_mst_substate_6_1_5 -// amec_mst_substate_6_1_6 -// amec_mst_substate_6_1_7 -// -// Description: master substate amec_mst_substate_6_1_0 -// master substate amec_mst_substate_6_1_1 -// master substate amec_mst_substate_6_1_2 -// master substate amec_mst_substate_6_1_3 -// master substate amec_mst_substate_6_1_4 -// master substate amec_mst_substate_6_1_5 -// master substate amec_mst_substate_6_1_6 -// master substate amec_mst_substate_6_1_7 -// -// Flow: FN= None -// -// End Function Specification -void amec_mst_sub_substate_6_1_0(void){AMEC_DBG("\tAMEC Master State 6.1.0\n");} -void amec_mst_sub_substate_6_1_1(void){AMEC_DBG("\tAMEC Master State 6.1.1\n");} -void amec_mst_sub_substate_6_1_2(void){AMEC_DBG("\tAMEC Master State 6.1.2\n");} -void amec_mst_sub_substate_6_1_3(void){AMEC_DBG("\tAMEC Master State 6.1.3\n");} -void amec_mst_sub_substate_6_1_4(void){AMEC_DBG("\tAMEC Master State 6.1.4\n");} -void amec_mst_sub_substate_6_1_5(void){AMEC_DBG("\tAMEC Master State 6.1.5\n");} -void amec_mst_sub_substate_6_1_6(void){AMEC_DBG("\tAMEC Master State 6.1.6\n");} -void amec_mst_sub_substate_6_1_7(void){AMEC_DBG("\tAMEC Master State 6.1.7\n");} /*----------------------------------------------------------------------------*/ /* End */ diff --git a/src/occ_405/amec/amec_master_smh.h b/src/occ_405/amec/amec_master_smh.h index 59563f6..23da57e 100755 --- a/src/occ_405/amec/amec_master_smh.h +++ b/src/occ_405/amec/amec_master_smh.h @@ -119,44 +119,7 @@ void amec_mst_state_5(void); void amec_mst_state_6(void); void amec_mst_state_7(void); -// Master SubState 0 -void amec_mst_substate_0_0(void); -void amec_mst_substate_0_1(void); -void amec_mst_substate_0_4(void); -void amec_mst_substate_0_7(void); - -// Master SubState 3 -void amec_mst_substate_3_0(void); -void amec_mst_substate_3_1(void); -void amec_mst_substate_3_2(void); -void amec_mst_substate_3_6(void); -void amec_mst_substate_3_7(void); - -// Master Sub-SubState 3 -void amec_mst_sub_substate_3_0_0(void); -void amec_mst_sub_substate_3_0_1(void); -void amec_mst_sub_substate_3_0_7(void); - -// Master SubState 6 -void amec_mst_substate_6_0(void); -void amec_mst_substate_6_1(void); -void amec_mst_substate_6_2(void); -void amec_mst_substate_6_3(void); -void amec_mst_substate_6_4(void); -void amec_mst_substate_6_5(void); -void amec_mst_substate_6_6(void); -void amec_mst_substate_6_7(void); - -void amec_mst_substate_3_0(void); -void amec_mst_substate_3_1(void); - -void amec_mst_sub_substate_6_1_0(void); -void amec_mst_sub_substate_6_1_1(void); -void amec_mst_sub_substate_6_1_2(void); -void amec_mst_sub_substate_6_1_3(void); -void amec_mst_sub_substate_6_1_4(void); -void amec_mst_sub_substate_6_1_5(void); -void amec_mst_sub_substate_6_1_6(void); -void amec_mst_sub_substate_6_1_7(void); +// Master SubState 5 (odd SubStates currently unused) +void amec_mst_substate_5_even(void); #endif diff --git a/src/occ_405/occ_sys_config.h b/src/occ_405/occ_sys_config.h index 951690a..9e5afcd 100755 --- a/src/occ_405/occ_sys_config.h +++ b/src/occ_405/occ_sys_config.h @@ -69,11 +69,6 @@ #define UPPER_LIMIT_PROC_FREQ_MHZ 6000 -//Number of samples per second for performance-related algorithms (e.g. UTILCy) -#define AMEC_DPS_SAMPLING_RATE 250 -//Time interval for averaging utilization and frequency (IPS algorithm) -#define AMEC_IPS_AVRG_INTERVAL 3 - // System Structures typedef union { @@ -256,7 +251,7 @@ typedef struct uint16_t table[OCC_MODE_COUNT]; // Table w/ freq for each mode uint8_t update_count; // uint8_t _reserved; // Align to 2 b/c we may use it in PBAX broadcast -} freqConfig_t; // @th040 +} freqConfig_t; // Power Cap Structures typedef struct diff --git a/src/occ_405/rtls/rtls.h b/src/occ_405/rtls/rtls.h index d7eaf5f..ad2b5fa 100755 --- a/src/occ_405/rtls/rtls.h +++ b/src/occ_405/rtls/rtls.h @@ -115,6 +115,16 @@ typedef struct #define SIMICS_MICS_PER_TICK 20000 // slow down RTL to 20ms for Simics #define DCOM_TX_APSS_WAIT_TIME G_dcom_tx_apss_wait_time +// core data collection time. All cores collected one time thru tick table +#define CORE_DATA_COLLECTION_US (MICS_PER_TICK * MAX_NUM_TICKS) +//Number of samples per second for performance-related algorithms (e.g. UTILCy) +#define AMEC_DPS_SAMPLING_RATE (1000000 / CORE_DATA_COLLECTION_US) +//Time interval for averaging utilization and frequency (IPS algorithm) 3 seconds +#define AMEC_IPS_AVRG_INTERVAL 3 +// NOTE: for IPS timings to work, need to make sure the check for amec_mst_ips_main() is at the same frequency +// i.e. core data is collected every CORE_DATA_COLLECTION_US the checking for amec_mst_ips_main() must be same. +// If core data collection time changes must adjust the checking for amec_mst_ips_main() to match + // The value of the current tick extern uint32_t G_current_tick; -- cgit v1.2.1