From f65ac6e260876471061373524ca33e79e0080825 Mon Sep 17 00:00:00 2001 From: Chris Cain Date: Mon, 25 Feb 2019 16:14:27 -0600 Subject: Add regs for PGPE debug Change-Id: I4a9cb7092548e7251806ae4e784fa5ee5a01fca2 CQ: SW457249 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72450 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles Reviewed-by: Douglas R. Gilbert Reviewed-by: William A. Bryan Reviewed-by: Christopher J. Cain --- src/occ_405/errl/errl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/occ_405/errl/errl.c b/src/occ_405/errl/errl.c index e40a9c6..0c705c5 100755 --- a/src/occ_405/errl/errl.c +++ b/src/occ_405/errl/errl.c @@ -386,6 +386,16 @@ errlHndl_t createPgpeErrl(const uint16_t i_modId, { TRAC_INFO("createPgpeErrl: Creating error log in slot [%d]", l_errSlot); + // Trace a few regs for PGPE debug + uint32_t l_oisr0_status; // OCC Interrupt Source 0 Register + uint32_t l_oisr1_status; // OCC Interrupt Source 1 Register + uint32_t l_occs2_status; // OCC Scratch 2 + l_oisr0_status = in32(OCB_OISR0); + l_oisr1_status = in32(OCB_OISR1); + l_occs2_status = in32(OCB_OCCS2); + TRAC_IMP("createPgpeErrl: OISR0=0x%08X, OISR1=0x%08X, OCCS2=0x%08X", + l_oisr0_status, l_oisr1_status, l_occs2_status); + // get slot pointer l_err = G_occErrSlots[ l_errSlot ]; -- cgit v1.2.1