From e00c5e2fad7d87e2a83076a45935bc114fabfe5b Mon Sep 17 00:00:00 2001 From: Doug Gilbert Date: Tue, 17 Oct 2017 14:26:56 -0500 Subject: Add pointers to all gpe trace buffers in gpe shared data. Change-Id: I4b326e97a54050faad127ab00fd5bf6532126fe6 RTC: 161456 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48519 Tested-by: FSP CI Jenkins Reviewed-by: Christopher J. Cain Reviewed-by: William A. Bryan --- src/include/p9_memmap_occ_sram.h | 44 +++++++++++++++++++++++++ src/occ_405/main.c | 69 +++++++++++++++++++++++++++++++++++----- 2 files changed, 105 insertions(+), 8 deletions(-) create mode 100644 src/include/p9_memmap_occ_sram.h diff --git a/src/include/p9_memmap_occ_sram.h b/src/include/p9_memmap_occ_sram.h new file mode 100644 index 0000000..be31637 --- /dev/null +++ b/src/include/p9_memmap_occ_sram.h @@ -0,0 +1,44 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/include/p9_memmap_occ_sram.h $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#if !defined(__P9_MEMMAP_OCC_SRAM_H__) +#define __P9_MEMMAP_OCC_SRAM_H__ + +#define OCC_SRAM_BASE_ADDR 0xFFF00000 + +#define GPE_DEBUG_PTRS_OFFSET 0x180 +#define PGPE_DEBUG_PTRS_OFFSET 0x200 +#define SGPE_DEBUG_PTRS_OFFSET 0x200 + +#define PK_TRACE_PTR_OFFSET 0x04 +#define PK_TRACE_SIZE_OFFSET 0x08 + +#define OCC_SRAM_IPC_REGION_SIZE (4 * 1024) +#define OCC_SRAM_GPE0_REGION_SIZE (60 * 1024) +#define OCC_SRAM_GPE1_REGION_SIZE (64 * 1024) + +#define GPE0_SRAM_BASE_ADDR OCC_SRAM_BASE_ADDR + OCC_SRAM_IPC_REGION_SIZE +#define GPE1_SRAM_BASE_ADDR GPE0_SRAM_BASE_ADDR + OCC_SRAM_GPE0_REGION_SIZE + +#endif diff --git a/src/occ_405/main.c b/src/occ_405/main.c index ca66eb2..938a4b4 100755 --- a/src/occ_405/main.c +++ b/src/occ_405/main.c @@ -61,6 +61,7 @@ #include #include "pgpe_service_codes.h" #include +#include "p9_memmap_occ_sram.h" // Used to indicate if OCC was started during IPL, in which case OCC's only // job is to look for checkstops. This flag is set by hostboot in OCC's header @@ -1172,25 +1173,23 @@ void read_hcode_headers() * Name: gpe_reset * * Description: Force a GPE to start executing instructions at the reset vector + * Only supports GPE0 and GPE1 * * End Function Specification */ void gpe_reset(uint32_t instance_id) { + #define XCR_CMD_HRESET 0x60000000 #define XCR_CMD_TOGGLE_XSR 0x40000000 #define XCR_CMD_RESUME 0x20000000 -#define GPE_SRAM_BASE 0xFFF00000 - uint32_t l_gpe_sram_addr = (instance_id * 0x10000) + GPE_SRAM_BASE; + uint32_t l_gpe_sram_addr = GPE0_SRAM_BASE_ADDR; - // GPE0 is at 0xFFF01000 - // GPE1 is at 0xFFF10000 - // GPE2 is at 0xFFF20000 - // GPE3 is at 0xFFF30000 - if(0 == instance_id) + if(1 == instance_id) { - l_gpe_sram_addr += 0x1000; + l_gpe_sram_addr = GPE1_SRAM_BASE_ADDR; + } out32(GPE_GPENIVPR(instance_id), l_gpe_sram_addr); @@ -1201,6 +1200,58 @@ void gpe_reset(uint32_t instance_id) out32(GPE_GPENXIXCR(instance_id), XCR_CMD_RESUME); } +/* + * Set up share_gpe_data struct + */ +void set_shared_gpe_data() +{ + uint32_t sram_addr; + + sram_addr = in32(GPE_GPENIVPR(OCCHW_INST_ID_GPE0)); + if(0 != sram_addr) + { + sram_addr += GPE_DEBUG_PTRS_OFFSET; + + G_shared_gpe_data.gpe0_tb_ptr = + *((uint32_t *)(sram_addr + PK_TRACE_PTR_OFFSET)); + G_shared_gpe_data.gpe0_tb_sz = + *((uint32_t *)(sram_addr + PK_TRACE_SIZE_OFFSET)); + } + + sram_addr = in32(GPE_GPENIVPR(OCCHW_INST_ID_GPE1)); + if(0 != sram_addr) + { + sram_addr += GPE_DEBUG_PTRS_OFFSET; + + G_shared_gpe_data.gpe1_tb_ptr = + *((uint32_t *)(sram_addr + PK_TRACE_PTR_OFFSET)); + G_shared_gpe_data.gpe1_tb_sz = + *((uint32_t *)(sram_addr + PK_TRACE_SIZE_OFFSET)); + } + + sram_addr = in32(GPE_GPENIVPR(OCCHW_INST_ID_GPE2)); + if(0 != sram_addr) + { + sram_addr += PGPE_DEBUG_PTRS_OFFSET; + + G_shared_gpe_data.pgpe_tb_ptr = + *((uint32_t *)(sram_addr + PK_TRACE_PTR_OFFSET)); + G_shared_gpe_data.pgpe_tb_sz = + *((uint32_t *)(sram_addr + PK_TRACE_SIZE_OFFSET)); + } + + sram_addr = in32(GPE_GPENIVPR(OCCHW_INST_ID_GPE3)); + if(0 != sram_addr) + { + sram_addr += SGPE_DEBUG_PTRS_OFFSET; + + G_shared_gpe_data.sgpe_tb_ptr = + *((uint32_t *)(sram_addr + PK_TRACE_PTR_OFFSET)); + G_shared_gpe_data.sgpe_tb_sz = + *((uint32_t *)(sram_addr + PK_TRACE_SIZE_OFFSET)); + } +} + /* * Function Specification * @@ -1253,6 +1304,8 @@ void occ_ipc_setup() MAIN_TRAC_INFO("GPE's taken out of reset"); + set_shared_gpe_data(); + }while(0); if(l_rc) -- cgit v1.2.1