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* Support for NVDIMMsChris Cain2018-09-261-2/+3
| | | | | | | | | | Change-Id: I8ccf44287bc72a73b16662ba29b71e731c70b30e RTC:173789 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65917 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* P9 Centaur sensor supportDoug Gilbert2018-03-281-3/+4
| | | | | | | | | Change-Id: Ia84bc7532482ca314c26bd0bb5bf48ad6ee9c410 RTC: 163359 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54989 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Enable hardware GPU power brakeDoug Gilbert2017-10-101-1/+2
| | | | | | | | | | Change-Id: I39ae6205cef6ae06cacc0eb2c8a0a4288b8081c8 RTC: 179617 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46800 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* 405 Side GPU Core Temp CollectionWilliam Bryan2017-08-251-0/+5
| | | | | | | | | Change-Id: Ia1b10f5208c49ba168dcf338f0cbeb2c4ab46971 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44982 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Initial 405 GPU supportmbroyles2017-08-141-1/+25
| | | | | | | Change-Id: I6e957ca1aa643d257274e99957df5b15ac8c889b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44254 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Memory Power Control when entering and exiting IPS (Idle Power Save)Wael El-Essawy2017-05-101-12/+13
| | | | | | | | | | | | | | | memory power control settings for IPS/default modes - as defined by memory config data packet version 0x21 - are applied to memory power control registers of all configured ports whenever the OCC enters/exits IPS, respectively. Change-Id: I56514bb8cbab80c6d4877edc74db96f3b011e523 RTC: 165546 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38294 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Infrastructure for 24x7 data collectionmbroyles2017-02-141-6/+8
| | | | | | | | | | Change-Id: I16277d8290f65ba489da1421783f3705be7281f4 RTC: 168729 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36043 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
* Implement task_poke_watchdogsWael El-Essawy2016-11-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | task_poke_watchdogs() should be called every 2ms (ticks 1 and 9) on both master and slaves while in observation and active state and do the following: 1. Every time called: Enable/Reset the OCC heartbeat: done by a write to OCB OCC Heartbeat Register (set count to 8ms) 2. Every time called: Reset memory deadman timer for 1 MCA (skip if not present and just wait until next call to check next MCA to keep same timing of reset per MCA regardless of # present) Resetting the deadman is done by reading one of the memory performance counters, use one at SCOM offset 0x13C. NOTE: Will take 16ms (8 MCAs x 2ms) to reset all memory timers, this is fine since the shortest time the deadman timeout can be configured to is 28ms 3. Every 4ms (on tick 1 only) : Verify PGPE is still functional by reading PGPE Beacon from SRAM if after 8ms (2 consecutive checks) there is no change to the PGPE Beacon count then log an error and request reset. In addition, this commit adds entries for the PGPE image header and shared SRAM in the TLB, and partially reads PGPE image header parameters. Change-Id: I9906102b3349506612d55c57e9f5c28441eaeb39 RTC: 154960 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31916 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Enable FW Timing SensorsWael El-Essawy2016-09-231-1/+2
| | | | | | | | | | | Enable scheduling of the GPE NOP task to do GPE timings and verify all sensors being updated in amec_update_fw_sensors() are being populated correctly. Change-Id: I623dd7518be9a8736e601c7d2fa748097a4d773a RTC: 141299 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29849 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Memory Temperature Control Loop (memory throttling)Wael El-Essawy2016-09-161-1/+2
| | | | | | | | | | | | * Memory throttling due to over temp * Throttle when reach timeout getting new temperature readings * Log error for temperature exceeding ERROR threshold Change-Id: I089c88aadba84e7296ad87b8cb87fa8c045ff912 RTC: 131188 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28933 Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: Wael El-Essawy <welessa@us.ibm.com>
* Remove IBM Confidential DisclaimersWilliam Bryan2016-08-021-0/+24
| | | | | | | | Change-Id: Ie3dcd5b6cee3e6b191cf136d30af634c9966318e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27718 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
* Implement code to read DIMM temperaturesChris Cain2016-01-271-1/+3
| | | | | | | | | | Change-Id: I98fc83ab1c78bd40241fe6e47a9ddeae24f78c38 RTC: 140093 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22770 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher Cain <cjcain@us.ibm.com>
* OCC: Init and start GPE1Chris Cain2015-09-241-0/+33
Change-Id: I2f1ef0a01497d46884eed25f1f63f9ebfcaf1da4 RTC: 133841 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20729 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
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