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RTC:131184
Change-Id: I2582a1eb9d599f700182f17047cc95accad03725
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51407
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: I62cf1be6a24e02a2cd59b75416d26596a4f2f81d
RTC: 169887
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45169
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
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memory power control settings for IPS/default modes - as defined by
memory config data packet version 0x21 - are applied to memory
power control registers of all configured ports whenever the OCC
enters/exits IPS, respectively.
Change-Id: I56514bb8cbab80c6d4877edc74db96f3b011e523
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38294
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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FIFO4 register requires a 4 byte read or will hang.
OCC will request 4 byte read, but only look at first 2 for temperature.
FIFO register can only read one byte per request which is less efficient.
Change-Id: Ia0bbbc70f5b7de76f1bea64279b2ff7dd5b5a861
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35974
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
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task_poke_watchdogs() should be called every 2ms (ticks 1 and 9) on both
master and slaves while in observation and active state and do the following:
1. Every time called: Enable/Reset the OCC heartbeat: done by a write to
OCB OCC Heartbeat Register (set count to 8ms)
2. Every time called: Reset memory deadman timer for 1 MCA (skip if not
present and just wait until next call to check next MCA to keep same
timing of reset per MCA regardless of # present) Resetting the deadman
is done by reading one of the memory performance counters, use one at
SCOM offset 0x13C. NOTE: Will take 16ms (8 MCAs x 2ms) to reset all
memory timers, this is fine since the shortest time the deadman timeout
can be configured to is 28ms
3. Every 4ms (on tick 1 only) : Verify PGPE is still functional by reading
PGPE Beacon from SRAM if after 8ms (2 consecutive checks) there is no
change to the PGPE Beacon count then log an error and request reset.
In addition, this commit adds entries for the PGPE image header and shared
SRAM in the TLB, and partially reads PGPE image header parameters.
Change-Id: I9906102b3349506612d55c57e9f5c28441eaeb39
RTC: 154960
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31916
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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* Memory throttling due to over temp
* Throttle when reach timeout getting new temperature readings
* Log error for temperature exceeding ERROR threshold
Change-Id: I089c88aadba84e7296ad87b8cb87fa8c045ff912
RTC: 131188
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28933
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Tested-by: Wael El-Essawy <welessa@us.ibm.com>
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