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* Timebase overflow issue in gpe0Doug Gilbert2017-10-191-0/+63
| | | | | | | | | | Change-Id: I555873ef13b5094f3499085f8aafb40ce4cc4320 CQ: SW403677 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48464 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Reduce number of checks when waiting for SPI completionmbroyles2017-07-261-14/+14
| | | | | | | | | | | | Fix GPE1 timing fw sensor Change-Id: I4e0d4256b0f55a5593b16237ace5bce73029f6da CQ: SW396887 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43706 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Enable Composite modeWilliam Bryan2017-04-261-0/+2
| | | | | | | | | Change-Id: I7235c414923079701fdf1392960b3fc48363bff0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38896 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* APSS P8/P9 Spec CompatibilityWilliam Bryan2017-02-231-7/+65
| | | | | | | | | Change-Id: Ib6cc0f872c22131b4268b3016d264460b7ef9098 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36450 Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Changes For P9 EnablementWilliam Bryan2017-02-151-1/+1
| | | | | | | | | | | Change-Id: I37e8174bcc6e99f602a66cff077ef41ad889b19c RTC:165351 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34949 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* OCC Active state changes required for SimicsChris Cain2016-10-141-24/+27
| | | | | | | | | Change-Id: Ic6e65bcddaefd5213042707feffcf1272133e532 RTC: 161266 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31190 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Enable APSS Composite ModeWilliam Bryan2016-09-301-7/+28
| | | | | | | | | | RTC:132559 Change-Id: Id66a6ee7083031f0a6a3364f4f01bdc9886ca638 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29070 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* OCC GPE0: Core Data Collection infrastructure in GPE0Wael El-Essawy2015-11-231-14/+14
| | | | | | | | | | | | Create IPC function for core data collection return dummy data at this point to allow 405 to schedule and "use" data back. Change-Id: I520e9333fa25e37127d6af693ad6f21da3431939 RTC: 131183 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22247 Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: Fadi Kassem <fmkassem@us.ibm.com>
* Create gpe error codes file, and use general GPE error codesWael El-Essawy2015-11-171-13/+13
| | | | | | | | Change-Id: I5bd957a3267cf7720fbaf5af31d9f6d432e7cd53 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21997 Tested-by: FSP CI Jenkins Reviewed-by: Christopher Cain <cjcain@us.ibm.com> Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
* Enable Sensor supportWael El-Essawy2015-11-111-3/+1
| | | | | | | | | | | | | | add necessary sensor, amec, and other files to the build list. add the task_amec_slave to the rtls tick tables modify the gpe request structures to reflect the new P9 design enrich the .dis files contects for better debugging Change-Id: Iae39bb1c430da56310478c24a28aad6dfbc6d6d9 RTC: 133865 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21789 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Implement busy wait and remove TOD accessWael El-Essawy2015-10-231-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | 1. Implement busy_wait() as an alternative to pk_sleep when APSS code runs in interrupt handlers. 2. Remove the TOD scom register access from the code, since it is not supported in simics yet. 3. Modify the calls to putscom_abs to take in register values rather than a pointer to register values, to be compatible with the new putscom code. 4. Eliminate code that endlessly triggers OCC and other GPEs, and add instead a counter with the number of ticks (250 usec) since last reset. Change-Id: I48414137434dfdc3cc4c038643536c1250fccbf2 RTC: 131177 RTC: 139105 RTC: 137703 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21269 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
* GPE0 error and ffdc codes, and remove most pk_haltsWael El-Essawy2015-09-081-156/+230
| | | | | | | | | | | | | | | | | | | | modified the wait_spi_completion function to make it args_t independent eliminated all scom/spi related pk_halts, left only ipc related pk_halt using new APSS_RC_XXX rc codes used apss_set_ffdc to set rc, ffdc, and address fields cleaned some comments added four PK traces to mark the start and completion of init routines removed gpe0 from PK traces, and added register address and scom operation added description for all functions deleted all assembly files Change-Id: I5a265c14b917b7c5d87647dad537725ee7f47001 RTC: 131177 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20277 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: Wael Elessawy <welessa@us.ibm.com>
* APSS init supportFadi Kassem2015-09-011-5/+4
| | | | | | | | | | Change-Id: I57df832e0611a097eac5285f52366061be091343 RTC:133242 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20250 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
* Wrote the three assembly GPE0 power measurement routine in CWael El-Essawy2015-08-281-3/+217
| | | | | | | | | | | | | | | | | | | created an apss_structs.h file to define common arguments data structure (between the OCC and GPE0) translated the _wait_for_adc_ops_complete assembly macro to C added the wait_spi.c file (probably rename in the future) eliminated tabs and trailing spaces and used linux development style cleaned comments, fixed errors added the ipc_send_cmd at the end of GPE0 functions used pss_constants to adopt the new SETENV SIM_OCC_SPIPSS_PCB_BASE RTC: 131177 Change-Id: I541f5e882dd65e0fafc87c3cc6eb95a32d87e466 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19981 Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
* Updates for IPC and GPE0mbroyles2015-08-041-0/+45
Change-Id: I8e31c3fdc0bf142e07ce2adc16abc585d63c8f82 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19524 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
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