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path: root/src/occ_405/ssx_app_cfg.h
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* Change trace buffer size from 32k to 8kDoug Gilbert2017-07-071-1/+1
| | | | | | | | | Change-Id: I54774ff4ea33105afa1bafc6636b9a8ee2c2f6ef Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33258 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* setup the GPE0/1 Halt and the System Checkstop interrupts properlyWael El-Essawy2017-04-251-3/+3
| | | | | | | | | | | Fix the ownership of these interrupts (assign it to the OCC), and set the interrupt type to level, and the interrupt polarity to high. Change-Id: I00c045736f4c3b196a95fdb9aa07f6f4dd66c8c6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38898 Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* PGPE init updatesChris Cain2017-04-131-0/+5
| | | | | | | | | | Change-Id: I0140184371619983fb38b27199f241efe7f30f16 RTC: 169886 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37770 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Changes For P9 EnablementWilliam Bryan2017-02-151-1/+2
| | | | | | | | | | | Change-Id: I37e8174bcc6e99f602a66cff077ef41ad889b19c RTC:165351 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34949 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* GPE IVPRs, disable OCC HW error and simics IOWilliam Bryan2016-12-211-1/+4
| | | | | | | | | | Change-Id: If9688f8dcbd44ab9a5658557ffe4a1b84a2fb1fe RTC:165351 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33745 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* SSX Runtime Environment CheckWilliam Bryan2016-10-111-1/+4
| | | | | | | | | | | RTC: 139829 Change-Id: Ic43ab936fd9d9b0d41270bbea50cd3969d9f8432 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30063 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Remove IBM Confidential DisclaimersWilliam Bryan2016-08-021-6/+1
| | | | | | | | Change-Id: Ie3dcd5b6cee3e6b191cf136d30af634c9966318e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27718 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
* Enable Master-slave OCC communicationWael El-Essawy2016-04-051-4/+0
| | | | | | | | | | Change-Id: I445072e20d599e30f80cc8059b3f3b2a956c453e RTC: 133154 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22005 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Fix Timing Discrepancy between OCC and PPEsWael El-Essawy2015-12-091-3/+3
| | | | | | | | | | | | | | Fix the code so that The whole OCC complex runs at the same (nest) frequency. This is the POR, which also solves the timing bug. Change-Id: Ib33c1951384b552fc4a44e07be09e9261a4b133d RTC: 139478 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22554 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Enable Slave DTS calculation and sensor update.Fadi Kassem2015-11-251-1/+0
| | | | | | | | Change-Id: I0feb572e650322326ce9a6c7b2affd9e58cd6b8d RTC:140183 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22303 Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: Wael Elessawy <welessa@us.ibm.com>
* Miscellaneous core data collection clean-upWilliam Bryan2015-11-241-2/+1
| | | | | | | | Change-Id: I3096b79b1c82ea4457dbf4f3875e8b91b47d8768 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22281 Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: Wael Elessawy <welessa@us.ibm.com>
* Core data initialization and 24-core supportWilliam Bryan2015-11-201-0/+1
| | | | | | | | | | RTC: 140187 RTC: 140186 Change-Id: I574acdc3933b4bc181a584226ea432b9abe72592 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22182 Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
* Update linkscript and init sectionsWilliam Bryan2015-11-171-0/+4
| | | | | | | | RTC: 134747 Change-Id: I3028b215f5560574e2ad5368f1a861bf46c61eb7 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21961 Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
* Remove applet supportWilliam Bryan2015-10-271-1/+1
| | | | | | | | | | | | | | 1. Removed most files related to applets 2. Converted sensor query list and command handler debug applets to functions. 3. Removed #includes of applet header files Change-Id: I410b3c68991e4fa6a7f542e5ee346a3d313f2a94 RTC: 137992 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21030 Tested-by: FSP CI Jenkins Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Enable tracingWilliam Bryan2015-08-271-0/+4
| | | | | | | | | | | | | | I've reverted the way we trace from SSX_TRACE to the P8 way More useful way of compiling for Simics vs HW RTC: 133155 Change-Id: I7ac3ce9ad71e36de0cf0050f14ff3d2423c9f75f Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20113 Tested-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Enabled FFDC and SimicsWilliam Bryan2015-08-261-0/+36
| | | | | | | | | | | | | | | | Also included: -- Some more cmdh files into the build -- Workaround for OCB Timer divider register in Simics -- Workaround to start APSS tasks until DCOM is back RTC: 133819 Change-Id: Ie19c2a544f64c40126c2bc4a0af6fabfe6430d21 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19998 Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
* OCC405 Stripped Down and CompilesWilliam Bryan2015-08-071-44/+142
| | | | | | | | Change-Id: Ic5c0536de429106975f5b5b0831c645d6f53e86c Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19650 Tested-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* new ssx and lib filesWilliam Bryan2015-08-031-0/+77
Change-Id: I2328b1e86d59e3788910687d762fb70ec680058f Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19503 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
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