| Commit message (Collapse) | Author | Age | Files | Lines |
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Correct DTS readings to be 8 bit with msb signed
Change-Id: Ib5d74535abd17696e9b30d63ccd28273ef4ddc61
CQ: SW410935
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50807
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
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Change-Id: I72436bd9ccfe2dba7e7c5f11f847fff2284ada00
CQ: SW407903
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49758
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Change-Id: Ica7272dc0fef3721b415fd5f72b1abf83397d341
CQ: SW407201
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49293
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: Ic8cda9a6b8b311057ba2c4f0d9dc7e228e700c27
CQ: SW404469
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49093
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
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Change-Id: If3ca5185bafda7d15e639e0f32c1b4ea3eba0c4c
RTC: 174964
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43959
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Fix GPE1 timing fw sensor
Change-Id: I4e0d4256b0f55a5593b16237ace5bce73029f6da
CQ: SW396887
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43706
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: I804cdf63879a2b80c9e14149e45ee665240c4a88
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43244
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: ILYA SMIRNOV <ismirno@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Correct power cap information in OPAL shared memory
Add non-zero error history counts to poll response
Fix Characterization to Active State change failure
Change-Id: I92b783b631e79786e6190a4def520fee32c2cc7c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43216
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: Ic53e27d851023d99440aa1bfbdf5307920af3397
RTC: 158812
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42512
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shawn M. McCarney <shawnmm@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: Iea8bc9321fa16829c64204461bad441561425cbc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42072
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: Id58a06378f3c0a7fd9fb436b96823eca15028031
RTC: 160889
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41513
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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-- Adds the use of GPIO_VR_HOT_MEM_PROC_0/1 in manufacturing mode.
-- Adds the ability to determine which GPUs are available in the system.
Change-Id: Ib86bca7b8ac279b044025a67002dc9e60ecd7c07
RTC:172166
RTC:155565
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39651
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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- Adjust fmax on slave to account for diff freq
- Remove SIMICS_FLAG_ISSUE (automic registers not working in simics)
- Cleanup traces
Change-Id: Ifc30333463bc5a1e44ec81bd365860460b802e71
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40461
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
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Change-Id: I0a7e9fe5c854ce17602c4c0293fd59f8c4a7c7b2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40419
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: I619513860541b7a98664b42894be5b9dd5f7ed30
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39811
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: Id709ec36d82a2b6c03b1a4b901cf64f45f241d36
RTC: 163934
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39562
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
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Change-Id: I1365d14bee48c287fcfd0faab8ba8a1a517e5bcb
RTC: 169886
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38107
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
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Change-Id: I97390f74d07b8ce8dad1519be4f7aacb3b9cef46
RTC:163356
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37299
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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the OCC maintains support for version 0x20
Change-Id: I06e637db202602e3823ffeceb56d482545b1016a
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36733
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Tested-by: Wael El-Essawy <welessa@us.ibm.com>
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Support for new characterization state changes used by manufacturing.
Observation state and new characterization state.
Details in version 0.10 OCC Interface Specifications.
Change-Id: I2ff0fc9327ad75e54c0a47cf42946e58f387522b
RTC: 163268
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35517
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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Change-Id: If7b7f175425301a4517f164d8b692067369b43f1
RTC: 163365
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35863
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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Change-Id: I16277d8290f65ba489da1421783f3705be7281f4
RTC: 168729
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36043
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
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To prevent in the future, users should run:
/esw/bin/bld/occScanForSRCs.pl
Change-Id: I98c5bb24a212bd7796ffb8319552fff7cff94f62
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35978
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Reviewed-by: Sheldon R. Bailey <baileysh@us.ibm.com>
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to avoid firestation failure
Change-Id: I90ab849b64f3dfaf732562ca91b29ff6d292f9f3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35524
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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1. Initialize Pstates global parameters (G_proc_fmax, G_proc_fmin,
G_khz_per_pstate and G_proc_pmin from the OCC Pstate Parameter
Block)
2. When frequency config data packet is received and OCC is NOT
already in Active state: Send IPC command to PGPE to set pState
clips to be wide open from min frequency to turbo
First verify min/max frequency from TMGT is within what
PGPE allows saved in G_proc_fmax and G_proc_fmin if not
within bounds trace and clip to G_proc_fmax/fmin)
3. Transition to active state: Send IPC command to PGPE to start
pState protocol (give correct data for OCC vs OPAL in control of
Pstates) and if OPAL system update OPAL shared memory with Pstate
information.
4. amec_slv_freq_smh(): Send IPC command to PGPE to set requested
pState (PowerVM) or set clips (OPAL).
5. Address all the TODO/TEMP/#if 0 in amec_freq.c either remove
or add RTC# for when it will be addressed
Change-Id: Ic323321b8c66945732a6b7345ad85d6f41a62edd
RTC: 130201
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33704
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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update the following in OPAL shared memory when any of these pieces
change:
* OCC State
* CPU Throttle status
* memory throttle status
* quick power drop
* power shifting ratio
* power cap type
* Min power cap
* Max power cap
* current power cap
*** When either throttle status bytes change alert OPAL of shared memory
interface change via setting SCOM bits 3 in the ext_intr_reason field
of OCC Misc register and bit 0 (core_ext_intr) to generate the interrupt.
Change-Id: Ic88a38aba4b84fb247389e712da2e326c2cd9c53
RTC: 130202
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32688
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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Change-Id: I9073d1bc30917495cdfdce33d6ab6d9f79e4745a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32496
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
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RTC:133842
Change-Id: I565a6f2e848652b7eddd3b319f9c3a411913074a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29804
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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RTC:148388
Change-Id: Iae66cd0a73032fa908eb96a149d4163397c2e275
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27781
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
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Change-Id: I08d76ac1db6e425a9690864f693f36cb848cead5
RTC: 153965
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28188
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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Enable processor thermal control loop.
Enable frequency votes due to thermal and error reading temperatures.
Verify The following:
*Error log generation when a proc reaches Error limit
*Reach throttle points when:
-- Processor reached over temperature limit
-- Processor temperature sensors timeout
enable transition to active mode
Change-Id: Iae24f64a872e031e1cf93ff0d9248d3fa3847ed7
RTC: 130210
RTC: 133942
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25458
Tested-by: FSP CI Jenkins
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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- Support all config data required for active state.
- Set 'active ready' bit in poll response when all config data has been received.
- Rewrite & rename proc_gpsm_pstate_initialize() - Delete GPSM, doesn't exist.
- Put in TODO call PGPE to enable pstates this will also be telling PGPE how to
set PMCR mode register (OCC control pstates or OPAL).
- Initialize globals for fmax, fmin, pmax and mhz_per_pstate with temporary hard
codes until PGPE is available.
- Call to "proc_pstate_initialize()" moved to state transition to observation
- Cleanup proc_freq2pstate()
- rewrite amec_slv_freq_smh()
- the calls to proc_set_core_bounds() and proc_set_core_pstate() will be
replaced with 1 IPC call to the PGPE to set pmin/pmax given all cores
or set pstate for all given cores.
- Remove all DCM related code.
Change-Id: I449d188b2cffc345afca19717dcbea037f159114
RTC:130224
RTC:150935
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23977
Tested-by: FSP CI Jenkins
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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The new P9 pba_region field in the PBA_MODE register is now 0b10
contrary to the P8 pba_region setting of 0b00.
Addresses have been corrected for Ping Pong communications,
HOMER Host Data, Sapphire Table, and HTMGT send and receive Buffers.
Replaced Sapphire legacy term with OPAL.
Defined COMMON_BASE_ADDRESS, and offset addresses relative to it.
modified HOMER_HD_OFFSET, OCC_HTMGT_CMD_OFFSET_HOMER,
OCC_HTMGT_RSP_OFFSET_HOMER, and OPAL_OFFSET_HOMER according
to new P9 specifications.
Change-Id: Ib233181c4ad1837b57c45144d1256b87799dc5bc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24085
Tested-by: FSP CI Jenkins
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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Change-Id: I445072e20d599e30f80cc8059b3f3b2a956c453e
RTC: 133154
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22005
Tested-by: FSP CI Jenkins
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Updating the code with HWP, simulated under simics with core and quad
DTSs, and verified trace results.
Change-Id: I914d65687f7c26d7073edae846de6a2c6f84cc02
RTC: 140095
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22929
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: Wael Elessawy <welessa@us.ibm.com>
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RTC: 140187
Change-Id: I3ad92658c18e76f58b3e7c9733e97cff437c7cdc
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22581
Tested-by: FSP CI Jenkins
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
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- maintain 8 core data collection states versus 16 rtls
ticks core scheduling scheme, utilizing substates to perform
4 ms full 24 cores data collection.
- introduce 4 substates, and distribute them over time (1,3,5,7)
- spread core data collection over 8 subsates, reading
3 cores data each time.
- eliminate gpe_bulk_core_data_t type
- reset dts elements using for loop instead of memset
- create amec_update_proc_core_group function and
G_sensor_update_pattern array to easily modify core data
sensors update pattern
Change-Id: Idd752c6ea77829ac308e2089f6582db472c8badc
RTC: 140094
RTC: 140183
RTC: 140186
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22347
Tested-by: Wael Elessawy <welessa@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: I0feb572e650322326ce9a6c7b2affd9e58cd6b8d
RTC:140183
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22303
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Tested-by: Wael Elessawy <welessa@us.ibm.com>
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Change-Id: I3096b79b1c82ea4457dbf4f3875e8b91b47d8768
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22281
Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Tested-by: Wael Elessawy <welessa@us.ibm.com>
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Create IPC function for core data collection return dummy
data at this point to allow 405 to schedule and "use" data back.
Change-Id: I520e9333fa25e37127d6af693ad6f21da3431939
RTC: 131183
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22247
Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Tested-by: Fadi Kassem <fmkassem@us.ibm.com>
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RTC: 140187
RTC: 140186
Change-Id: I574acdc3933b4bc181a584226ea432b9abe72592
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22182
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Tested-by: Fadi Kassem <fmkassem@us.ibm.com>
Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
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add necessary sensor, amec, and other files to the build list.
add the task_amec_slave to the rtls tick tables
modify the gpe request structures to reflect the new P9 design
enrich the .dis files contects for better debugging
Change-Id: Iae39bb1c430da56310478c24a28aad6dfbc6d6d9
RTC: 133865
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21789
Tested-by: FSP CI Jenkins
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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1. Removed most files related to applets
2. Converted sensor query list and command handler debug applets
to functions.
3. Removed #includes of applet header files
Change-Id: I410b3c68991e4fa6a7f542e5ee346a3d313f2a94
RTC: 137992
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21030
Tested-by: FSP CI Jenkins
Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
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Change-Id: Ic5c0536de429106975f5b5b0831c645d6f53e86c
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19650
Tested-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
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Change-Id: I2328b1e86d59e3788910687d762fb70ec680058f
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19503
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>
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