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Change-Id: I9073d1bc30917495cdfdce33d6ab6d9f79e4745a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32496
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
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Change-Id: Ie3dcd5b6cee3e6b191cf136d30af634c9966318e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27718
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
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- Support all config data required for active state.
- Set 'active ready' bit in poll response when all config data has been received.
- Rewrite & rename proc_gpsm_pstate_initialize() - Delete GPSM, doesn't exist.
- Put in TODO call PGPE to enable pstates this will also be telling PGPE how to
set PMCR mode register (OCC control pstates or OPAL).
- Initialize globals for fmax, fmin, pmax and mhz_per_pstate with temporary hard
codes until PGPE is available.
- Call to "proc_pstate_initialize()" moved to state transition to observation
- Cleanup proc_freq2pstate()
- rewrite amec_slv_freq_smh()
- the calls to proc_set_core_bounds() and proc_set_core_pstate() will be
replaced with 1 IPC call to the PGPE to set pmin/pmax given all cores
or set pstate for all given cores.
- Remove all DCM related code.
Change-Id: I449d188b2cffc345afca19717dcbea037f159114
RTC:130224
RTC:150935
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23977
Tested-by: FSP CI Jenkins
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
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Change-Id: I791df565b9277ab3cd29d1616fd0affac2c3e68d
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19499
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>
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