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-rw-r--r--src/common/centaur_configuration.h245
-rw-r--r--src/common/centaur_structs.h64
-rw-r--r--src/common/gpe_err.h2
-rw-r--r--src/common/ipc_func_ids.h3
-rw-r--r--src/include/centaur_mem_data.h174
-rw-r--r--src/include/gpe_pba_parms.h53
-rw-r--r--src/include/registers/centaur_firmware_registers.h1589
-rw-r--r--src/include/registers/centaur_register_addresses.h77
-rw-r--r--src/include/registers/mcs_firmware_registers.h102
-rw-r--r--src/include/registers/p9_misc_scom_addresses.h28
-rw-r--r--src/include/registers/pba_firmware_constants.h2
-rw-r--r--src/include/registers/pba_register_addresses.h67
-rw-r--r--src/lib/ppc405lib/chip_config.h14
-rw-r--r--src/occ_405/amec/amec_sensors_centaur.c43
-rwxr-xr-xsrc/occ_405/amec/amec_slave_smh.c35
-rwxr-xr-xsrc/occ_405/cent/centaur_control.c100
-rwxr-xr-xsrc/occ_405/cent/centaur_control.h5
-rwxr-xr-xsrc/occ_405/cent/centaur_data.c416
-rwxr-xr-xsrc/occ_405/cent/centaur_data.h26
-rwxr-xr-xsrc/occ_405/cmdh/cmdh_dbug_cmd.c14
-rwxr-xr-xsrc/occ_405/cmdh/cmdh_fsp_cmds.c31
-rwxr-xr-xsrc/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c23
-rwxr-xr-xsrc/occ_405/dimm/dimm.c383
-rw-r--r--src/occ_405/mem/memory.c40
-rwxr-xr-xsrc/occ_405/occbuildname.c2
-rwxr-xr-xsrc/occ_405/sensor/sensor_enum.h2
-rw-r--r--src/occ_gpe1/gpe1_main.c3
-rw-r--r--src/occ_gpe1/gpe_centaur.c89
-rw-r--r--src/occ_gpe1/gpe_centaur.h53
-rw-r--r--src/occ_gpe1/gpe_centaur_configuration.c538
-rw-r--r--src/occ_gpe1/gpe_centaur_scom.c571
-rw-r--r--src/occ_gpe1/img_defs.mk27
-rw-r--r--src/occ_gpe1/ipc_func_tables.c7
-rw-r--r--src/occ_gpe1/topfiles.mk3
34 files changed, 4183 insertions, 648 deletions
diff --git a/src/common/centaur_configuration.h b/src/common/centaur_configuration.h
new file mode 100644
index 0000000..43f2792
--- /dev/null
+++ b/src/common/centaur_configuration.h
@@ -0,0 +1,245 @@
+#if !defined(__CENTAUR_CONFIGURATION_H__)
+#define __CENTAUR_CONFIGURATION_H__
+
+//#include "occhw_common.h"
+#include "gpe_pba_parms.h"
+#include "centaur_firmware_registers.h"
+
+#define OCCHW_NCENTAUR 8
+
+/// Error return codes set/returned by centaur_configuration_create()
+
+typedef enum
+{
+
+ CENTAUR_INVALID_ARGUMENT = 0x007ccc01,
+ CENTAUR_MCSMODE0_SCOM_FAILURE = 0x007ccc02,
+ CENTAUR_MCSMODE0_19_FAILURE = 0x007ccc03,
+ CENTAUR_ADDRESS_27_FAILURE = 0x007ccc04,
+ CENTAUR_MULTIPLE_DESIGNATED_SYNC = 0x007ccc05,
+ CENTAUR_NO_DESIGNATED_SYNC = 0x007ccc06,
+ CENTAUR_BAR_MASK_ERROR = 0x007ccc07,
+ CENTAUR_CONFIGURATION_FAILED = 0x007ccc08,
+ CENTAUR_DATA_SETUP_ERROR = 0x007ccc09,
+ CENTAUR_SCOM_SETUP_ERROR = 0x007ccc0a,
+ CENTAUR_NOT_CONFIGURED = 0x007ccc0b,
+ CENTAUR_MASK_ERROR = 0x007ccc0c,
+ CENTAUR_READ_TPC_ID_FAILURE = 0x007ccc0d,
+ CENTAUR_BARMSKN_PUTSCOM_FAILURE = 0x007ccc0e,
+ CENTAUR_BARN_PUTSCOM_FAILURE = 0x007ccc0f,
+ CENTAUR_BARMSKN_GETSCOM_FAILURE = 0x007ccc10,
+ CENTAUR_BARN_GETSCOM_FAILURE = 0x007ccc11,
+} CentaurConfigurationCreateRc;
+
+/**
+ * Definition of the CentaurConfiguration data.
+ * @note location must be 8-byte aligned, size must be multiple of 8 bytes.
+ */
+typedef struct
+{
+
+ /// Centaur base addresses for in-band operations
+ ///
+ uint64_t baseAddress[OCCHW_NCENTAUR];
+
+ /// Contents of Centaur device id registers
+ ///
+ /// These are the device ID SCOMs (0x000f000f) read from configured
+ /// Centaur during initialization. A 0 value indicates an unconfigured
+ /// Centaur. These values are deconstructed by the memory buffer (mb)
+ /// APIs mb_id(), mb_chip_type() and mb_ec_level().
+ centaur_device_id_t deviceId[OCCHW_NCENTAUR];
+
+ /// The image of the PBA slave control register to use for the SYNC command
+ ///
+ /// The PowerBus address used to accomplish a Centaur SYNC is
+ /// constant. To simplify the procedures the PBA slave control register
+ /// (containing the extended address portion of the address) is
+ /// pre-computed and stored here.
+ ///
+ /// \note One and Only one of the MCS units can be targeted with SYNC
+ /// commands. The design includes a private bus connecting all MCS on the
+ /// chip that allows this "SYNC master" to broadcast the SYNC to all other
+ /// MCS on the chip.
+ pba_slvctln_t syncSlaveControl;
+
+ /// A GpePbaParms parameter block for gpe_mem_data()
+ ///
+ /// This parameter block is set up in advance and used by the GPE
+ /// procedure gpe_mem_data(). Given the complexity of accessing Centaur
+ /// sensors and SCOM through the PBA it is simpler to set these up ahead
+ /// of time and simply have the GPE procedures access preconfigured global
+ /// data. The \a dataParms and \a scomParms members are distinguished by
+ /// the different way the PBA slave needs to be configured to access
+ /// either the Centaur sensor cache or Centaur SCOMs.
+ GpePbaParms dataParms;
+
+ /// A GpePbaParms parameter block for IPC_ST_CENTAUR_SCOM().
+ GpePbaParms scomParms;
+
+ /// A "chip configuration" bit mask denoting valid Centaur
+ ///
+ /// It shoud always be true that a bit denoting a configured Centaur is
+ /// associated with a non-0 \a baseAddress and vice-versa.
+ uint32_t config;
+
+
+ /// The final return code from centaur_configuration_create().
+ /// @see CentaurConfigurationCreateRc
+ /// If initialization fails then this value can be used to diagnose what
+ /// happend. This field should be statically initialized to a non-0 value
+ /// (CENTAUR_NOT_CONFIGURED) and can then be checked against 0 to
+ /// determine if the structure has been correctly initialized.
+ int32_t configRc;
+
+} CentaurConfiguration_t __attribute__((aligned(8)));
+
+// Moved CentaurGetMemDataParms_t to centaur_structs.h
+
+typedef struct
+{
+ union
+ {
+ struct
+ {
+ uint32_t scom;
+ uint8_t reserved;
+ uint8_t errorFlags;
+ uint8_t instanceNumber;
+ uint8_t commandType;
+ };
+ uint64_t command;
+ };
+ uint64_t mask;
+ union
+ {
+ uint64_t data;
+ struct
+ {
+ uint32_t unused;
+ uint64_t* pData;
+ };
+ };
+} scomList_t;
+
+
+// Centaur Scom Return Codes
+enum
+{
+ // rc 1 - 7 reserved from scom rc
+ CENTAUR_INVALID_SCOM = 100,
+ CENTAUR_GET_MEM_DATA_COLLECT_INVALID = 200,
+ CENTAUR_GET_MEM_DATA_UPDATE_INVALID = 201,
+ CENTAUR_GET_MEM_DATA_DIED = 202,
+ CENTAUR_CHANNEL_CHECKSTOP = 203,
+};
+
+// Centaur Scom Operations
+typedef enum
+{
+ /// No operation
+ CENTAUR_SCOM_NOP,
+
+ /// Read from SCOM, depositing read data into the \a data field of the
+ /// scomList_t.
+ CENTAUR_SCOM_READ,
+
+ /// Write to SCOM, taking write data from the \a data field of the scomList_t.
+ CENTAUR_SCOM_WRITE,
+
+ /// Read-Modify-Write.
+ ///
+ /// This operation first reads the SCOM. Bits under the \a mask field of the
+ /// scomList_t are then cleared in the read data. The masked read data is then
+ /// ORed with the contents of the \a data field of the scomList_t and the
+ /// result is written back to the SCOM address.
+ ///
+ /// \note This command \e does \e not apply the mask to the data from the \a
+ /// data field of the scomList_t. The caller should do this (if necessary)
+ /// when setting up the scomList_t.
+ ///
+ /// \note The procedures do not provide a way to distinguish errors that may
+ /// have occurred on the initial read vs. those that may have occurred on the
+ /// subsequenct write.
+ CENTAUR_SCOM_RMW,
+
+ /// For IPC_ST_CENTAUR_SCOM(), the \a data field of the scomList_t contains a
+ /// 32-bit pointer (cast to a uint64_t) to an array of PGP_NCENTAUR uint64_t
+ /// values. SCOM read data for each configured Centaur (MCS) is deposited in
+ /// this array. Array entries for unconfigured Centaur are zeroed.
+ CENTAUR_SCOM_READ_VECTOR,
+
+ /// For IPC_ST_CENTAUR_SCOM(), write the \a data field of the scomList_t to
+ /// all configured Centaur. Currently unsupported for gpe_scom_p8().
+ CENTAUR_SCOM_WRITE_ALL,
+
+ /// For IPC_ST_CENTAUR_SCOM(), perform read-modify write for all configured
+ /// Centaur. Currently unsupported for gpe_scom_p8().
+ CENTAUR_SCOM_RMW_ALL,
+
+ /// Issue a generic Centaur SYNC
+ ///
+ /// This command is only valid for IPC_ST_CENTAUR_SCOM(). This command creates
+ /// and issues a generic SYNC command to Centaur. The caller is completely
+ /// responsible for creating the contents of the data packet sent as part of
+ /// the Centaur SYNC. The data packet is taken verbatim from the \a data field
+ /// of the scomList_t, and sent to the MCS designated as the SYNC MCS in the
+ /// global G_centaurConfiguration. For further details see the comments with
+ /// the procedure IPC_ST_CENTAUR_SCOM() and the CentaurConfiguration structure.
+ CENTAUR_SCOM_CENTAUR_SYNC,
+
+ /// Issue a Centaur SYNC to all configured Centaur
+ ///
+ /// This command is only valid for IPC_ST_CENTAUR_SCOM(). This command creates
+ /// and issues a SYNC command to all configured Centaur. The data packet is
+ /// taken from the \a data field of the scomList_t, and sent to the MCS
+ /// designated as the SYNC MCS in the global G_centaurConfiguration. The
+ /// caller is responsible for setting the SYNC command bits (bits 8:N); The
+ /// procedure will fill bits 0:7 with a mask of all configured Centaur. For
+ /// further details see the comments with the procedure IPC_ST_CENTAUR_SCOM() and
+ /// the CentaurConfiguration structure.
+ CENTAUR_SCOM_CENTAUR_SYNC_ALL,
+
+} centaur_scom_operation_t;
+
+
+// BAR and PBA_SLAVE assigned to gpe1 centaur
+// - @see POWER Energy Management Hcode/HWP spec
+#define PBA_BAR_CENTAUR 1
+#define PBA_SLAVE_CENTAUR 2
+
+// This is used to setup CentaurConfiguration.config field
+#define CHIP_CONFIG_MCS_BASE 16
+#define CHIP_CONFIG_MCS(n) \
+ ((0x80000000ul >> CHIP_CONFIG_MCS_BASE) >> (n))
+
+#define CHIP_CONFIG_CENTAUR_BASE 24
+#define CHIP_CONFIG_CENTAUR(n) \
+ ((0x80000000ul >> CHIP_CONFIG_CENTAUR_BASE) >> (n))
+
+#endif
+
+/// \defgroup centaur_sync_commands Centaur SYNC Command Bits
+///
+/// The Centaur SYNC command is an 8-byte word written to a specific in-band
+/// address. SYNC commands are generated by the gpe_scom_centaur() procedure
+/// in response to the GPE_SCOM_CENTAUR_SYNC and GPE_SCOM_CENTAUR_SYNC_ALL
+/// commands (which see).
+///
+/// \note From the MCS Unit Workbook: Note that only the N/M Throttle sync
+/// command will be used operationally in P-series, although if will be
+/// possible to test all the sync commands in P-series lab testing. Z-series
+/// will use all specified sync command types. ... Valid combinations of bits
+/// (8:15) are: b00000000, bVVVVVV0V, and b00000010, where V = 0 or 1.
+///
+/// @{
+
+#define CENTAUR_GENERATE_REFRESH_COUNTER_SYNC 0x0080000000000000ull
+#define CENTAUR_RESET_CALIBRATION_COUNTER_1_SYNC 0x0040000000000000ull
+#define CENTAUR_RESET_CALIBRATION_COUNTER_2_SYNC 0x0020000000000000ull
+#define CENTAUR_RESET_CALIBRATION_COUNTER_3_SYNC 0x0010000000000000ull
+#define CENTAUR_RESET_N_M_THROTTLE_COUNTER_SYNC 0x0008000000000000ull
+#define CENTAUR_RESET_MB_TIMEBASE_SYNC 0x0004000000000000ull
+#define CENTAUR_SUPER_SYNC 0x0002000000000000ull
+#define CENTAUR_MYSTERY_SYNC 0x0001000000000000ull
+
diff --git a/src/common/centaur_structs.h b/src/common/centaur_structs.h
new file mode 100644
index 0000000..c0b7a66
--- /dev/null
+++ b/src/common/centaur_structs.h
@@ -0,0 +1,64 @@
+#if !defined(_CENTAUR_STRUCTS_H)
+#define _CENTAUR_STRUCTS_H
+
+#include "stdint.h"
+#include "gpe_export.h"
+#include "centaur_configuration.h"
+
+// IPC message payload for call to IPC_ST_CENTAUR_INIT_FUNCID
+typedef struct
+{
+ GpeErrorStruct error;
+ CentaurConfiguration_t * centaurConfiguration;
+
+} CentaurConfigParms_t;
+
+// IPC message payload for call to IPC_ST_CENTAUR_SCOM_FUNCID
+typedef struct
+{
+ GpeErrorStruct error;
+
+ /**
+ * Input: The SCOM list
+ * This is a pointer to an array of scomList_t objects
+ * describing the sequence of commands to execute.
+ */
+ scomList_t* scomList;
+
+ /**
+ * Input: The number of entries in the scomList.
+ * @note It is considered an error if \a entries is 0, under the
+ * assumption that the caller must have neglected to initialize the
+ * structure.
+ */
+ int entries;
+
+} CentaurScomParms_t;
+
+// IPC message payload for call to IPC_ST_CENTAUR_DATA_FUNCID
+typedef struct
+{
+ GpeErrorStruct error;
+
+ /**
+ * The index (0 .. PGP_NCENTAUR - 1) of the Centaur whose sensor cache
+ * data to collect, or -1 to bypass collection.
+ */
+ int collect;
+
+ /**
+ * The index (0 .. PGP_NCENTAUR - 1) of the Centaur to "poke" to cause it
+ * to begin collecting the next round of data into its sensor cache, or
+ * -1 to bypass updating
+ */
+ int update;
+
+ /**
+ * Pointer to data collected. Needs to be set if collect != -1
+ * otherwise it's not used.
+ */
+ uint64_t * data;
+} CentaurGetMemDataParms_t;
+
+
+#endif
diff --git a/src/common/gpe_err.h b/src/common/gpe_err.h
index 9dfe1ca..66e9295 100644
--- a/src/common/gpe_err.h
+++ b/src/common/gpe_err.h
@@ -42,6 +42,8 @@
// Memory Power Control Error
#define GPE_RC_INVALID_MEM_PWR_CTL 0x20 // Invalid value for the memory power control command
+// Centaur mem ctl codes
+#define GPE_RC_CONFIG_DATA_NULL_PTR 0x30 // centaurConfiguration data ptr NULL
// APSS Specific gpe return Codes
#define GPE_RC_INVALID_APSS_MODE 0x40 // OCC requested undefined APSS mode
diff --git a/src/common/ipc_func_ids.h b/src/common/ipc_func_ids.h
index 4684937..df4d9ed 100644
--- a/src/common/ipc_func_ids.h
+++ b/src/common/ipc_func_ids.h
@@ -75,6 +75,9 @@ IPC_FUNCIDS_TABLE_START
IPC_FUNC_ID(IPC_ST_MEM_POWER_CONTROL_FUNCID)
IPC_FUNC_ID(IPC_ST_GPU_SM_FUNCID)
IPC_FUNC_ID(IPC_ST_GPE_GPU_INIT_FUNCID)
+ IPC_FUNC_ID(IPC_ST_CENTAUR_SCOM_FUNCID)
+ IPC_FUNC_ID(IPC_ST_CENTAUR_DATA_FUNCID)
+ IPC_FUNC_ID(IPC_ST_CENTAUR_INIT_FUNCID)
IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE1)
//Functions that are only supported by GPE2 should be defined here
diff --git a/src/include/centaur_mem_data.h b/src/include/centaur_mem_data.h
new file mode 100644
index 0000000..e97e3c6
--- /dev/null
+++ b/src/include/centaur_mem_data.h
@@ -0,0 +1,174 @@
+#if !defined(__CENTAUR_MEM_DATA_H__)
+#define __CENTAUR_MEM_DATA_H__
+typedef union {
+ uint16_t value;
+ struct {
+ uint16_t value;
+ } fields;
+} centaur_sensor_t;
+
+/// The layout of a Centaur DIMM sensor
+///
+/// Mnemonic macros for the 2-bit status codes (DIMM_SENSOR_STATUS_*) are
+/// currently defined in ssx/pgp/pgp_common.h
+///
+/// \todo Waiting for more info from Centaur team on how to interpret
+
+typedef union {
+ uint16_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint16_t crit_trip : 1;
+ uint16_t alarm_trip : 1;
+ uint16_t below_trip : 1;
+ uint16_t sign_bit : 1;
+ uint16_t temperature : 8;
+ uint16_t temp_fraction : 2;
+ uint16_t status : 2;
+#else
+ uint16_t status : 2;
+ uint16_t temp_fraction : 2;
+ uint16_t temperature : 8;
+ uint16_t sign_bit : 1;
+ uint16_t below_trip : 1;
+ uint16_t alarm_trip : 1;
+ uint16_t crit_trip : 1;
+#endif
+ } fields;
+} centaur_dimm_sensor_t;
+
+/// The layout of the status bits of the sensor cache line
+///
+/// The sensor cache-line aggregator gets each element of the sensor cache
+/// line by an internal SCOM. The individual PCB return codes for each SCOM
+/// are collected here (3 bits each) - note that many of the 32-bit registers
+/// come back in a single 64-bit internal SCOM. Normally this register will
+/// always read as 0 indicating all data was collected successfully. The PCB
+/// error codes (PCB_ERROR_*) are currently defined in ssx/pgp/pgp_common.h.
+
+typedef union {
+ uint64_t value;
+ struct {
+#ifdef _BIG_ENDIAN
+ uint64_t mba01_rw : 3; /// mba01_rd[+ wr]
+ uint64_t mba01_ap : 3; /// mba01_act[+ powerups]
+ uint64_t mba23_rw : 3; /// mba23_rd[+ wr]
+ uint64_t mba23_ap : 3; /// mba23_act[+ powerups]
+ uint64_t mba_sc : 3; /// mba01[+ 23]_spec_cancels
+ uint64_t lp2_exits : 3; /// lp2_exits
+ uint64_t frame_count : 3; /// frame_count
+ uint64_t mba01_chrw : 3; /// mba01_cache_hits_rd[+ wr]
+ uint64_t mba23_chrw : 3; /// mba23_cache_hits_rd[+ wr]
+ uint64_t mba01_iac_bl : 3; /// mba01_intreq_arr_cnt_base[+ low]
+ uint64_t mba01_iac_mh : 3; /// mba01_intreq_arr_cnt_med[+ high]
+ uint64_t mba23_iac_bl : 3; /// mba23_intreq_arr_cnt_base[+ low]
+ uint64_t mba23_iac_mh : 3; /// mba23_intreq_arr_cnt_med[+ high]
+ uint64_t iac_high_latency : 3; /// intereq_arr_cnt_high_latency
+ uint64_t centaur01 : 3; /// centaur_thermal_sensor[0 - 1]
+ uint64_t dimm03 : 3; /// dimm_thermal_sensor[0 - 3]
+ uint64_t dimm47 : 3; /// dimm_thermal_sensor[4 - 7]
+ uint64_t reserved : 13;
+#else
+ uint64_t reserved : 13;
+ uint64_t dimm47 : 3; /// dimm_thermal_sensor[4 - 7]
+ uint64_t dimm03 : 3; /// dimm_thermal_sensor[0 - 3]
+ uint64_t centaur01 : 3; /// centaur_thermal_sensor[0 - 1]
+ uint64_t iac_high_latency : 3; /// intereq_arr_cnt_high_latency
+ uint64_t mba23_iac_mh : 3; /// mba23_intreq_arr_cnt_med[+ high]
+ uint64_t mba23_iac_bl : 3; /// mba23_intreq_arr_cnt_base[+ low]
+ uint64_t mba01_iac_mh : 3; /// mba01_intreq_arr_cnt_med[+ high]
+ uint64_t mba01_iac_bl : 3; /// mba01_intreq_arr_cnt_base[+ low]
+ uint64_t mba23_chrw : 3; /// mba23_cache_hits_rd[+ wr]
+ uint64_t mba01_chrw : 3; /// mba01_cache_hits_rd[+ wr]
+ uint64_t frame_count : 3; /// frame_count
+ uint64_t lp2_exits : 3; /// lp2_exits
+ uint64_t mba_sc : 3; /// mba01[+ 23]_spec_cancels
+ uint64_t mba23_ap : 3; /// mba23_act[+ powerups]
+ uint64_t mba23_rw : 3; /// mba23_rd[+ wr]
+ uint64_t mba01_ap : 3; /// mba01_act[+ powerups]
+ uint64_t mba01_rw : 3; /// mba01_rd[+ wr]
+#endif
+ } fields;
+} centaur_scom_status_t;
+
+/// The layout of the Centaur sensor cache line
+
+
+typedef struct {
+ uint32_t mba01_rd; // PP1/MBA01 Reads
+ uint32_t mba01_wr; // PP1/MBA01 Writes
+ uint32_t mba01_act; // PP1/MBA01 Activations
+ uint32_t mba01_powerups; // PP1/MBA01 PowerUps
+
+ uint32_t mba23_rd; // PP2/MBA23 Reads
+ uint32_t mba23_wr; // PP2/MBA23 Writes
+ uint32_t mba23_act; // PP2/MBA23 Activations
+ uint32_t mba23_powerups; // PP2/MBA23 PowerUps
+
+ uint32_t mba01_spec_cancels; // PP1/MBA01 Speculative Cancels
+ uint32_t mba23_spec_cancels; // PP2/MBA23 Speculative Cancels
+#ifdef _BIG_ENDIAN
+ uint32_t eventn :4; // EVENTN
+ uint32_t reserved_0 :20; // Reserved
+ uint32_t lp2_exits :8; // LP2 Exits
+#else
+ uint32_t lp2_exits :8; // LP2 Exits
+ uint32_t reserved_0 :20; // Reserved
+ uint32_t eventn :4; // EVENTN
+#endif
+ uint32_t frame_count; // Frame Count (timestamp)
+
+ uint32_t mba01_cache_hits_rd; // PP1/MBA01 Cache Hits Reads
+ uint32_t mba01_cache_hits_wr; // PP1/MBA01 Cache Hits Writes
+ uint32_t mba23_cache_hits_rd; // PP2/MBA23 Cache Hits Reads
+ uint32_t mba23_cache_hits_wr; // PP2/MBA23 Cache Hits Writes
+
+ uint32_t mba01_intreq_arr_cnt_base; // PP1/MBA01 Inter-Req Arrival Count Base
+ uint32_t mba01_intreq_arr_cnt_low; // PP1/MBA01 Inter-Req Arrival Count Low
+ uint32_t mba01_intreq_arr_cnt_med; // PP1/MBA01 Inter-Req Arrival Count Med
+ uint32_t mba01_intreq_arr_cnt_high; // PP1/MBA01 Inter-Req Arrival Count High
+
+ uint32_t mba23_intreq_arr_cnt_base; // PP2/MBA23 Inter-Req Arrival Count Base
+ uint32_t mba23_intreq_arr_cnt_low; // PP2/MBA23 Inter-Req Arrival Count Low
+ uint32_t mba23_intreq_arr_cnt_med; // PP2/MBA23 Inter-Req Arrival Count Med
+ uint32_t mba23_intreq_arr_cnt_high; // PP2/MBA23 Inter-Req Arrival Count High
+
+ uint32_t intreq_arr_cnt_high_latency; // Inter-Req Arrival Count High Latency
+ centaur_sensor_t centaur_thermal_sensor[2]; // Centaur Thermal Sensors 0-1
+ centaur_dimm_sensor_t dimm_thermal_sensor[8]; // DIMM Thermal Sensors 0-7
+ centaur_scom_status_t status; // Aggregated internal SCOM status
+} MemDataSensorCache;
+
+typedef struct {
+ MemDataSensorCache scache; // OCC Centaur Sensor Cache Line (128 bytes)
+} CentaurMemData;
+
+/// \defgroup gpe_mem_data_rc gpe_get_mem_data() Error Return Codes
+///
+/// The gpe_get_mem_data() procedure deposits a non-0 return code into the \a
+/// rc field of its parameter structure in the event of failure. Note that the
+/// procedure stops on the first failure, and in particular the TOD timestamp
+/// is not valid in the event of failure.
+///
+/// @{
+
+/// The global G_centaurConfiguration is not valid
+#define CENTAUR_GET_MEM_DATA_NOT_CONFIGURED 4
+
+/// The workaround for HW256773 failed. To diagnose the failure look at the
+/// 'rc' field of the global variable G_hw256773.
+#define CENTAUR_GET_MEM_DATA_HW256773_FAILED 5
+
+/// This code is established in the RC field prior to collecting the Centaur
+/// sensor cache data. If this RC is observed on a hard failure it most likely
+/// indicates an error assiciated with the Centaur whose data was being
+/// collected.
+#define CENTAUR_GET_MEM_DATA_SENSOR_CACHE_FAILED 6
+
+/// This code is established in the RC field prior to "poking" the Centaur (if
+/// any) that is being updated this pass. If this RC is observed on a hard
+/// failure it most likely indicates an error associated with the Centaur
+/// being updated.
+#define CENTAUR_GET_MEM_DATA_UPDATE_FAILED 7
+
+#endif
diff --git a/src/include/gpe_pba_parms.h b/src/include/gpe_pba_parms.h
new file mode 100644
index 0000000..35cbb94
--- /dev/null
+++ b/src/include/gpe_pba_parms.h
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/common/pmlib/include/gpe_pba_parms.h $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#if !defined(__GPE_PBA_PARMS_H__)
+#define __GPE_PBA_PARMS_H__
+
+#include <stdint.h>
+#include "pba_register_addresses.h"
+#include "pba_firmware_registers.h"
+
+typedef struct
+{
+
+ /// The 32-bit OCI address of the PBA_SLVCTLn register to set up
+ uint32_t slvctl_address;
+
+ /// The slave id (0 - 3)
+ uint32_t slave_id;
+ /// An image of the relevant parts of the PBA_SLVCTLn register in effect
+ /// for this procedure
+ //pba_slvctln_t slvctl;
+ pba_slvctln_t slvctl;
+
+ /// The mask in effect for this update of the PBA_SLVCTL
+ //pba_slvctln_t mask;
+ pba_slvctln_t mask;
+
+ /// The value to write to the PBA_SLVRST register to reset the slave
+ //pba_slvrst_t slvrst;
+ pba_slvrst_t slvrst;
+
+ /// The bit to AND-poll to check for slave reset in progress
+ //pba_slvrst_t slvrst_in_progress;
+ pba_slvrst_t slvrst_in_progress;
+
+} GpePbaParms;
+
+#endif
diff --git a/src/include/registers/centaur_firmware_registers.h b/src/include/registers/centaur_firmware_registers.h
new file mode 100644
index 0000000..7ec99be
--- /dev/null
+++ b/src/include/registers/centaur_firmware_registers.h
@@ -0,0 +1,1589 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/common/pmlib/include/registers/centaur_firmware_registers.h $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __CENTAUR_FIRMWARE_REGISTERS_H__
+#define __CENTAUR_FIRMWARE_REGISTERS_H__
+
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+ #ifdef __ASSEMBLER__
+ #define SIXTYFOUR_BIT_CONSTANT(x) x
+ #else
+ #define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+ #endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+
+
+
+typedef union centaur_device_id
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t cfam_id : 32;
+ uint64_t module_id : 2;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t module_id : 2;
+ uint64_t cfam_id : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_device_id_t;
+
+
+
+typedef union centaur_mbs_fir_reg
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_fir_reg_t;
+
+
+
+typedef union centaur_mbs_fir_reg_and
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_fir_reg_and_t;
+
+
+
+typedef union centaur_mbs_fir_reg_or
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_fir_reg_or_t;
+
+
+
+typedef union centaur_mbs_fir_mask_reg
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_fir_mask_reg_t;
+
+
+
+typedef union centaur_mbs_fir_mask_reg_and
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_fir_mask_reg_and_t;
+
+
+
+typedef union centaur_mbs_fir_mask_reg_or
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_fir_mask_reg_or_t;
+
+
+
+typedef union centaur_mbs_fir_action0_reg
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_fir_action0_reg_t;
+
+
+
+typedef union centaur_mbs_firact1
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t host_protocol_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t external_timeout : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t lru_error : 1;
+ uint64_t edram_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t _reserved0 : 30;
+#else
+ uint64_t _reserved0 : 30;
+ uint64_t internal_scom_error_copy : 1;
+ uint64_t internal_scom_error : 1;
+ uint64_t spare_fir31 : 1;
+ uint64_t spare_fir30 : 1;
+ uint64_t dir_purge_ce : 1;
+ uint64_t srb_buffer_sue : 1;
+ uint64_t srb_buffer_ue : 1;
+ uint64_t srb_buffer_ce : 1;
+ uint64_t occ_inband_write_error : 1;
+ uint64_t occ_inband_read_error : 1;
+ uint64_t host_inband_write_error : 1;
+ uint64_t host_inband_read_error : 1;
+ uint64_t emergency_throttle_set : 1;
+ uint64_t edram_error : 1;
+ uint64_t lru_error : 1;
+ uint64_t dir_all_members_deleted : 1;
+ uint64_t dir_member_deleted : 1;
+ uint64_t dir_ue : 1;
+ uint64_t dir_ce : 1;
+ uint64_t cache_co_sue : 1;
+ uint64_t cache_co_ue : 1;
+ uint64_t cache_co_ce : 1;
+ uint64_t cache_srw_sue : 1;
+ uint64_t cache_srw_ue : 1;
+ uint64_t cache_srw_ce : 1;
+ uint64_t int_parity_error : 1;
+ uint64_t int_buffer_sue : 1;
+ uint64_t int_buffer_ue : 1;
+ uint64_t int_buffer_ce : 1;
+ uint64_t internal_timeout : 1;
+ uint64_t external_timeout : 1;
+ uint64_t invalid_address_error : 1;
+ uint64_t int_protocol_error : 1;
+ uint64_t host_protocol_error : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbs_firact1_t;
+
+
+
+typedef union centaur_mbscfgq
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t eccbp_exit_sel : 1;
+ uint64_t dram_ecc_bypass_dis : 1;
+ uint64_t mbs_scom_wat_trigger : 1;
+ uint64_t mbs_prq_ref_avoidance_en : 1;
+ uint64_t reserved4_6 : 3;
+ uint64_t occ_deadman_timer_sel : 4;
+ uint64_t sync_fsync_mba_strobe_en : 1;
+ uint64_t hca_timebase_op_mode : 1;
+ uint64_t hca_local_timer_inc_select : 3;
+ uint64_t mbs_01_rdtag_delay : 4;
+ uint64_t mbs_01_rdtag_force_dead_cycle : 1;
+ uint64_t sync_lat_pol_01 : 1;
+ uint64_t sync_lat_adj_01 : 2;
+ uint64_t mbs_23_rdtag_delay : 4;
+ uint64_t mbs_23_rdtag_force_dead_cycle : 1;
+ uint64_t sync_lat_pol_23 : 1;
+ uint64_t sync_lat_adj_23 : 2;
+ uint64_t _reserved0 : 32;
+#else
+ uint64_t _reserved0 : 32;
+ uint64_t sync_lat_adj_23 : 2;
+ uint64_t sync_lat_pol_23 : 1;
+ uint64_t mbs_23_rdtag_force_dead_cycle : 1;
+ uint64_t mbs_23_rdtag_delay : 4;
+ uint64_t sync_lat_adj_01 : 2;
+ uint64_t sync_lat_pol_01 : 1;
+ uint64_t mbs_01_rdtag_force_dead_cycle : 1;
+ uint64_t mbs_01_rdtag_delay : 4;
+ uint64_t hca_local_timer_inc_select : 3;
+ uint64_t hca_timebase_op_mode : 1;
+ uint64_t sync_fsync_mba_strobe_en : 1;
+ uint64_t occ_deadman_timer_sel : 4;
+ uint64_t reserved4_6 : 3;
+ uint64_t mbs_prq_ref_avoidance_en : 1;
+ uint64_t mbs_scom_wat_trigger : 1;
+ uint64_t dram_ecc_bypass_dis : 1;
+ uint64_t eccbp_exit_sel : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbscfgq_t;
+
+
+
+typedef union centaur_mbsemerthroq
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t emergency_throttle_ip : 1;
+ uint64_t _reserved0 : 63;
+#else
+ uint64_t _reserved0 : 63;
+ uint64_t emergency_throttle_ip : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbsemerthroq_t;
+
+
+
+typedef union centaur_mbsocc01hq
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_01_rd_hit : 32;
+ uint64_t occ_01_wr_hit : 32;
+#else
+ uint64_t occ_01_wr_hit : 32;
+ uint64_t occ_01_rd_hit : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbsocc01hq_t;
+
+
+
+typedef union centaur_mbsocc23hq
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_23_rd_hit : 32;
+ uint64_t occ_23_wr_hit : 32;
+#else
+ uint64_t occ_23_wr_hit : 32;
+ uint64_t occ_23_rd_hit : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbsocc23hq_t;
+
+
+
+typedef union centaur_mbsoccitcq
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_cent_idle_th_cnt : 32;
+ uint64_t _reserved0 : 32;
+#else
+ uint64_t _reserved0 : 32;
+ uint64_t occ_cent_idle_th_cnt : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbsoccitcq_t;
+
+
+
+typedef union centaur_mbsoccscanq
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t occ_01_spec_can : 32;
+ uint64_t occ_23_spec_can : 32;
+#else
+ uint64_t occ_23_spec_can : 32;
+ uint64_t occ_01_spec_can : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbsoccscanq_t;
+
+
+
+typedef union centaur_mbarpc0qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t cfg_lp2_entry_req : 1;
+ uint64_t cfg_lp2_state : 1;
+ uint64_t cfg_min_max_domains_enable : 1;
+ uint64_t cfg_min_max_domains : 3;
+ uint64_t cfg_pup_avail : 5;
+ uint64_t cfg_pdn_pup : 5;
+ uint64_t cfg_pup_pdn : 5;
+ uint64_t reserved0 : 1;
+ uint64_t cfg_min_domain_reduction_enable : 1;
+ uint64_t cfg_min_domain_reduction_on_time : 10;
+ uint64_t cfg_pup_after_activate_wait_enable : 1;
+ uint64_t cfg_pup_after_activate_wait_time : 8;
+ uint64_t cfg_force_spare_pup : 1;
+ uint64_t _reserved0 : 21;
+#else
+ uint64_t _reserved0 : 21;
+ uint64_t cfg_force_spare_pup : 1;
+ uint64_t cfg_pup_after_activate_wait_time : 8;
+ uint64_t cfg_pup_after_activate_wait_enable : 1;
+ uint64_t cfg_min_domain_reduction_on_time : 10;
+ uint64_t cfg_min_domain_reduction_enable : 1;
+ uint64_t reserved0 : 1;
+ uint64_t cfg_pup_pdn : 5;
+ uint64_t cfg_pdn_pup : 5;
+ uint64_t cfg_pup_avail : 5;
+ uint64_t cfg_min_max_domains : 3;
+ uint64_t cfg_min_max_domains_enable : 1;
+ uint64_t cfg_lp2_state : 1;
+ uint64_t cfg_lp2_entry_req : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbarpc0qn_t;
+
+
+
+typedef union centaur_mba_farb3qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t cfg_nm_n_per_mba : 15;
+ uint64_t cfg_nm_n_per_chip : 16;
+ uint64_t cfg_nm_m : 14;
+ uint64_t cfg_nm_ras_weight : 3;
+ uint64_t cfg_nm_cas_weight : 3;
+ uint64_t cfg_nm_per_slot_enabled : 1;
+ uint64_t cfg_nm_count_other_mba_dis : 1;
+ uint64_t _reserved0 : 11;
+#else
+ uint64_t _reserved0 : 11;
+ uint64_t cfg_nm_count_other_mba_dis : 1;
+ uint64_t cfg_nm_per_slot_enabled : 1;
+ uint64_t cfg_nm_cas_weight : 3;
+ uint64_t cfg_nm_ras_weight : 3;
+ uint64_t cfg_nm_m : 14;
+ uint64_t cfg_nm_n_per_chip : 16;
+ uint64_t cfg_nm_n_per_mba : 15;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mba_farb3qn_t;
+
+
+
+typedef union centaur_mbapcn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t mode_hp_sub_cnt : 1;
+ uint64_t mode_lp_sub_cnt : 1;
+ uint64_t mode_static_idle_dly : 5;
+ uint64_t mode_emer_min_max_domain : 3;
+ uint64_t mode_pup_all_wr_pending : 2;
+ uint64_t mode_lp_ref_sim_enq : 1;
+ uint64_t _reserved0 : 51;
+#else
+ uint64_t _reserved0 : 51;
+ uint64_t mode_lp_ref_sim_enq : 1;
+ uint64_t mode_pup_all_wr_pending : 2;
+ uint64_t mode_emer_min_max_domain : 3;
+ uint64_t mode_static_idle_dly : 5;
+ uint64_t mode_lp_sub_cnt : 1;
+ uint64_t mode_hp_sub_cnt : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbapcn_t;
+
+
+
+typedef union centaur_mbasrqn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t emergency_m : 14;
+ uint64_t emergency_n : 15;
+ uint64_t _reserved0 : 35;
+#else
+ uint64_t _reserved0 : 35;
+ uint64_t emergency_n : 15;
+ uint64_t emergency_m : 14;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_mbasrqn_t;
+
+
+
+typedef union centaur_pmu0qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t read_count : 32;
+ uint64_t write_count : 32;
+#else
+ uint64_t write_count : 32;
+ uint64_t read_count : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_pmu0qn_t;
+
+
+
+typedef union centaur_pmu1qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t activate_count : 32;
+ uint64_t pu_counts : 32;
+#else
+ uint64_t pu_counts : 32;
+ uint64_t activate_count : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_pmu1qn_t;
+
+
+
+typedef union centaur_pmu2qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t frame_count : 32;
+ uint64_t _reserved0 : 32;
+#else
+ uint64_t _reserved0 : 32;
+ uint64_t frame_count : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_pmu2qn_t;
+
+
+
+typedef union centaur_pmu3qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t low_idle_threshold : 16;
+ uint64_t med_idle_threshold : 16;
+ uint64_t high_idle_threshold : 32;
+#else
+ uint64_t high_idle_threshold : 32;
+ uint64_t med_idle_threshold : 16;
+ uint64_t low_idle_threshold : 16;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_pmu3qn_t;
+
+
+
+typedef union centaur_pmu4qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t base_idle_count : 32;
+ uint64_t low_idle_count : 32;
+#else
+ uint64_t low_idle_count : 32;
+ uint64_t base_idle_count : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_pmu4qn_t;
+
+
+
+typedef union centaur_pmu5qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t med_idle_count : 32;
+ uint64_t high_idle_count : 32;
+#else
+ uint64_t high_idle_count : 32;
+ uint64_t med_idle_count : 32;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_pmu5qn_t;
+
+
+
+typedef union centaur_pmu6qn
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t total_gap_counts : 18;
+ uint64_t specific_gap_counts : 18;
+ uint64_t gap_length_adder : 3;
+ uint64_t specific_gap_condition : 4;
+ uint64_t cmd_to_cmd_count : 18;
+ uint64_t command_pattern_to_count : 3;
+#else
+ uint64_t command_pattern_to_count : 3;
+ uint64_t cmd_to_cmd_count : 18;
+ uint64_t specific_gap_condition : 4;
+ uint64_t gap_length_adder : 3;
+ uint64_t specific_gap_counts : 18;
+ uint64_t total_gap_counts : 18;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_pmu6qn_t;
+
+
+
+typedef union centaur_sensor_cache_data0_3
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t crittrip0 : 1;
+ uint64_t abovetrip0 : 1;
+ uint64_t belowtrip0 : 1;
+ uint64_t signbit0 : 1;
+ uint64_t temperature0 : 8;
+ uint64_t temp_frac0 : 2;
+ uint64_t status0 : 2;
+ uint64_t crittrip1 : 1;
+ uint64_t abovetrip1 : 1;
+ uint64_t belowtrip1 : 1;
+ uint64_t signbit1 : 1;
+ uint64_t temperature1 : 8;
+ uint64_t temp_frac1 : 2;
+ uint64_t status1 : 2;
+ uint64_t crittrip2 : 1;
+ uint64_t abovetrip2 : 1;
+ uint64_t belowtrip2 : 1;
+ uint64_t signbit2 : 1;
+ uint64_t temperature2 : 8;
+ uint64_t temp_frac2 : 2;
+ uint64_t status2 : 2;
+ uint64_t crittrip3 : 1;
+ uint64_t abovetrip3 : 1;
+ uint64_t belowtrip3 : 1;
+ uint64_t signbit3 : 1;
+ uint64_t temperature3 : 8;
+ uint64_t temp_frac3 : 2;
+ uint64_t status3 : 2;
+#else
+ uint64_t status3 : 2;
+ uint64_t temp_frac3 : 2;
+ uint64_t temperature3 : 8;
+ uint64_t signbit3 : 1;
+ uint64_t belowtrip3 : 1;
+ uint64_t abovetrip3 : 1;
+ uint64_t crittrip3 : 1;
+ uint64_t status2 : 2;
+ uint64_t temp_frac2 : 2;
+ uint64_t temperature2 : 8;
+ uint64_t signbit2 : 1;
+ uint64_t belowtrip2 : 1;
+ uint64_t abovetrip2 : 1;
+ uint64_t crittrip2 : 1;
+ uint64_t status1 : 2;
+ uint64_t temp_frac1 : 2;
+ uint64_t temperature1 : 8;
+ uint64_t signbit1 : 1;
+ uint64_t belowtrip1 : 1;
+ uint64_t abovetrip1 : 1;
+ uint64_t crittrip1 : 1;
+ uint64_t status0 : 2;
+ uint64_t temp_frac0 : 2;
+ uint64_t temperature0 : 8;
+ uint64_t signbit0 : 1;
+ uint64_t belowtrip0 : 1;
+ uint64_t abovetrip0 : 1;
+ uint64_t crittrip0 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_sensor_cache_data0_3_t;
+
+
+
+typedef union centaur_sensor_cache_data4_7
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t crittrip4 : 1;
+ uint64_t abovetrip4 : 1;
+ uint64_t belowtrip4 : 1;
+ uint64_t signbit4 : 1;
+ uint64_t temperature4 : 8;
+ uint64_t temp_frac4 : 2;
+ uint64_t status4 : 2;
+ uint64_t crittrip5 : 1;
+ uint64_t abovetrip5 : 1;
+ uint64_t belowtrip5 : 1;
+ uint64_t signbit5 : 1;
+ uint64_t temperature5 : 8;
+ uint64_t temp_frac5 : 2;
+ uint64_t status5 : 2;
+ uint64_t crittrip6 : 1;
+ uint64_t abovetrip6 : 1;
+ uint64_t belowtrip6 : 1;
+ uint64_t signbit6 : 1;
+ uint64_t temperature6 : 8;
+ uint64_t temp_frac6 : 2;
+ uint64_t status6 : 2;
+ uint64_t crittrip7 : 1;
+ uint64_t abovetrip7 : 1;
+ uint64_t belowtrip7 : 1;
+ uint64_t signbit7 : 1;
+ uint64_t temperature7 : 8;
+ uint64_t temp_frac7 : 2;
+ uint64_t status7 : 2;
+#else
+ uint64_t status7 : 2;
+ uint64_t temp_frac7 : 2;
+ uint64_t temperature7 : 8;
+ uint64_t signbit7 : 1;
+ uint64_t belowtrip7 : 1;
+ uint64_t abovetrip7 : 1;
+ uint64_t crittrip7 : 1;
+ uint64_t status6 : 2;
+ uint64_t temp_frac6 : 2;
+ uint64_t temperature6 : 8;
+ uint64_t signbit6 : 1;
+ uint64_t belowtrip6 : 1;
+ uint64_t abovetrip6 : 1;
+ uint64_t crittrip6 : 1;
+ uint64_t status5 : 2;
+ uint64_t temp_frac5 : 2;
+ uint64_t temperature5 : 8;
+ uint64_t signbit5 : 1;
+ uint64_t belowtrip5 : 1;
+ uint64_t abovetrip5 : 1;
+ uint64_t crittrip5 : 1;
+ uint64_t status4 : 2;
+ uint64_t temp_frac4 : 2;
+ uint64_t temperature4 : 8;
+ uint64_t signbit4 : 1;
+ uint64_t belowtrip4 : 1;
+ uint64_t abovetrip4 : 1;
+ uint64_t crittrip4 : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_sensor_cache_data4_7_t;
+
+
+
+typedef union centaur_dts_thermal_sensor_results
+{
+
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t dts0 : 12;
+ uint64_t thermal_trip0 : 2;
+ uint64_t spare0 : 1;
+ uint64_t valid0 : 1;
+ uint64_t dts1 : 12;
+ uint64_t thermal_trip1 : 2;
+ uint64_t spare1 : 1;
+ uint64_t valid1 : 1;
+ uint64_t _reserved0 : 32;
+#else
+ uint64_t _reserved0 : 32;
+ uint64_t valid1 : 1;
+ uint64_t spare1 : 1;
+ uint64_t thermal_trip1 : 2;
+ uint64_t dts1 : 12;
+ uint64_t valid0 : 1;
+ uint64_t spare0 : 1;
+ uint64_t thermal_trip0 : 2;
+ uint64_t dts0 : 12;
+#endif // _BIG_ENDIAN
+ } fields;
+} centaur_dts_thermal_sensor_results_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __CENTAUR_FIRMWARE_REGISTERS_H__
+
diff --git a/src/include/registers/centaur_register_addresses.h b/src/include/registers/centaur_register_addresses.h
new file mode 100644
index 0000000..56dd415
--- /dev/null
+++ b/src/include/registers/centaur_register_addresses.h
@@ -0,0 +1,77 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/common/pmlib/include/registers/centaur_register_addresses.h $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#ifndef __CENTAUR_REGISTER_ADDRESSES_H__
+#define __CENTAUR_REGISTER_ADDRESSES_H__
+
+
+/// \file centaur_register_addresses.h
+/// \brief Symbolic addresses for the CENTAUR unit
+//
+//See MC chiplet
+//MBA_FARBnQ where (0 <= n <= 8) 0x7010913
+
+#define CENTAUR_PIB_BASE 0
+#define CENTAUR_DEVICE_ID 0x000f000f
+#define CENTAUR_MBS_FIR_REG 0x02011400
+#define CENTAUR_MBS_FIR_REG_AND 0x02011401
+#define CENTAUR_MBS_FIR_REG_OR 0x02011402
+#define CENTAUR_MBS_FIR_MASK_REG 0x02011403
+#define CENTAUR_MBS_FIR_MASK_REG_AND 0x02011404
+#define CENTAUR_MBS_FIR_MASK_REG_OR 0x02011405
+#define CENTAUR_MBS_FIR_ACTION0_REG 0x02011406
+#define CENTAUR_MBS_FIRACT1 0x02011407
+#define CENTAUR_MBSCFGQ 0x02011411
+#define CENTAUR_MBSEMERTHROQ 0x0201142d
+#define CENTAUR_MBSOCC01HQ 0x02011429
+#define CENTAUR_MBSOCC23HQ 0x0201142a
+#define CENTAUR_MBSOCCITCQ 0x02011428
+#define CENTAUR_MBSOCCSCANQ 0x0201142b
+#define CENTAUR_MBARPC0QN(n) (CENTAUR_MBARPC0Q0 + ((CENTAUR_MBARPC0Q1 - CENTAUR_MBARPC0Q0) * (n)))
+#define CENTAUR_MBARPC0Q0 0x03010434
+#define CENTAUR_MBARPC0Q1 0x03010c34
+#define CENTAUR_MBA_FARB3QN(n) (CENTAUR_MBA_FARB3Q0 + ((CENTAUR_MBA_FARB3Q1 - CENTAUR_MBA_FARB3Q0) * (n)))
+#define CENTAUR_MBA_FARB3Q0 0x03010416
+#define CENTAUR_MBA_FARB3Q1 0x03010c16
+#define CENTAUR_PMU0QN(n) (CENTAUR_PMU0Q0 + ((CENTAUR_PMU0Q1 - CENTAUR_PMU0Q0) * (n)))
+#define CENTAUR_PMU0Q0 0x03010437
+#define CENTAUR_PMU0Q1 0x03010c37
+#define CENTAUR_PMU1QN(n) (CENTAUR_PMU1Q0 + ((CENTAUR_PMU1Q1 - CENTAUR_PMU1Q0) * (n)))
+#define CENTAUR_PMU1Q0 0x03010438
+#define CENTAUR_PMU1Q1 0x03010c38
+#define CENTAUR_PMU2QN(n) (CENTAUR_PMU2Q0 + ((CENTAUR_PMU2Q1 - CENTAUR_PMU2Q0) * (n)))
+#define CENTAUR_PMU2Q0 0x03010439
+#define CENTAUR_PMU2Q1 0x03010c39
+#define CENTAUR_PMU3QN(n) (CENTAUR_PMU3Q0 + ((CENTAUR_PMU3Q1 - CENTAUR_PMU3Q0) * (n)))
+#define CENTAUR_PMU3Q0 0x0301043a
+#define CENTAUR_PMU3Q1 0x03010c3a
+#define CENTAUR_PMU4QN(n) (CENTAUR_PMU4Q0 + ((CENTAUR_PMU4Q1 - CENTAUR_PMU4Q0) * (n)))
+#define CENTAUR_PMU4Q0 0x0301043b
+#define CENTAUR_PMU4Q1 0x03010c3b
+#define CENTAUR_PMU5QN(n) (CENTAUR_PMU5Q0 + ((CENTAUR_PMU5Q1 - CENTAUR_PMU5Q0) * (n)))
+#define CENTAUR_PMU5Q0 0x0301043c
+#define CENTAUR_PMU5Q1 0x03010c3c
+#define CENTAUR_PMU6QN(n) (CENTAUR_PMU6Q0 + ((CENTAUR_PMU6Q1 - CENTAUR_PMU6Q0) * (n)))
+#define CENTAUR_PMU6Q0 0x0301043d
+#define CENTAUR_PMU6Q1 0x03010c3d
+#define CENTAUR_SENSOR_CACHE_DATA0_3 0x020115ca
+#define CENTAUR_SENSOR_CACHE_DATA4_7 0x020115cb
+#define CENTAUR_DTS_THERMAL_SENSOR_RESULTS 0x02050000
+
+#endif // __CENTAUR_REGISTER_ADDRESSES_H__
+
diff --git a/src/include/registers/mcs_firmware_registers.h b/src/include/registers/mcs_firmware_registers.h
new file mode 100644
index 0000000..6071755
--- /dev/null
+++ b/src/include/registers/mcs_firmware_registers.h
@@ -0,0 +1,102 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/common/pmlib/include/registers/mcs_firmware_registers.h $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#if !defined(__MCS_FIRWARE_REGISTERS_H__)
+#define __MCS_FIRWARE_REGISTERS_H__
+
+typedef union mcfgpr
+{
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t mcfgprq_valid : 1;
+ uint64_t reserved0 : 2;
+ uint64_t disable_extended_bar : 1 ; // low = P9 mode
+ uint64_t mcfgprq_base_address : 31;
+ uint64_t _reserved0 : 29;
+#else
+ uint64_t _reserved0 : 29;
+ uint64_t mcfgprq_base_address : 31;
+ uint64_t disable_extended_bar : 1 ; // low = p9 mode
+ uint64_t reserved0 : 2;
+ uint64_t mcfgprq_valid : 1;
+#endif // _BIG_ENDIAN
+ } fields;
+} mcfgpr_t;
+
+
+typedef union mcsmode0
+{
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved0 : 64;
+#else
+ uint64_t reserved0 : 64;
+#endif
+ } fields;
+} mcsmode0_t;
+
+
+
+typedef union mcifir
+{
+ uint64_t value;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint32_t high_order;
+ uint32_t low_order;
+#else
+ uint32_t low_order;
+ uint32_t high_order;
+#endif // _BIG_ENDIAN
+ } words;
+ struct
+ {
+#ifdef _BIG_ENDIAN
+ uint64_t reserved0 : 64;
+#else
+ uint64_t reserved0 : 64;
+#endif // _BIG_ENDIAN
+ } fields;
+} mcifir_t;
+
+#endif
diff --git a/src/include/registers/p9_misc_scom_addresses.h b/src/include/registers/p9_misc_scom_addresses.h
index 480bff4..1f2dd81 100644
--- a/src/include/registers/p9_misc_scom_addresses.h
+++ b/src/include/registers/p9_misc_scom_addresses.h
@@ -7,4 +7,32 @@
#define PU_GPIO_OUTPUT_CLR 0x000B0053
#define PU_GPIO_OUTPUT_EN 0x000B0054
+
+// Found in Cumulus nest "MC Fault Isolation Register"
+#define MCS_0_MCFIR 0x05010800
+#define MCS_1_MCFIR 0x05010880
+#define MCS_2_MCFIR 0x03010800
+#define MCS_3_MCFIR 0x03010880
+
+// found in Cumulus nest "MC Mode0 Register"
+#define MCS_0_MCMODE0 0x05010811
+#define MCS_1_MCMODE0 0x05010891
+#define MCS_2_MCMODE0 0x03010811
+#define MCS_3_MCMODE0 0x03010891
+
+// found in Cumulus nest "MC Primary Memory Configuration Register"
+#define MCS_0_MCRSVDE 0x0501080E
+#define MCS_0_MCRSVDF 0x0501080F
+#define MCS_1_MCRSVDE 0x0501088E
+#define MCS_1_MCRSVDF 0x0501088F
+#define MCS_2_MCRSVDE 0x0301080E
+#define MCS_2_MCRSVDF 0x0301080F
+#define MCS_3_MCRSVDE 0x0301088E
+#define MCS_3_MCRSVDF 0x0301088F
+
+// MC Primary Memory Configuration Register (MCFGP)
+#define MCS_0_MCFGP 0x0501080A
+#define MCS_1_MCFGP 0x0501088A
+#define MCS_2_MCFGP 0x0301080A
+#define MCS_3_MCFGP 0x0301088A
#endif
diff --git a/src/include/registers/pba_firmware_constants.h b/src/include/registers/pba_firmware_constants.h
index 0fa6e19..2b462c2 100644
--- a/src/include/registers/pba_firmware_constants.h
+++ b/src/include/registers/pba_firmware_constants.h
@@ -24,7 +24,7 @@
/* IBM_PROLOG_END_TAG */
#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
-#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
+#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x00fffffffff00000)
#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
diff --git a/src/include/registers/pba_register_addresses.h b/src/include/registers/pba_register_addresses.h
index 10db791..7b00385 100644
--- a/src/include/registers/pba_register_addresses.h
+++ b/src/include/registers/pba_register_addresses.h
@@ -31,7 +31,7 @@
// *** WARNING *** - This file is generated automatically, do not edit.
-
+// OCI addresses
#define PBA_OCI_BASE 0xC0040000
#define PBA_MODE 0xc0040000
#define PBA_SLVRST 0xc0040008
@@ -44,11 +44,13 @@
#define PBA_BCDE_SET 0xc0040088
#define PBA_BCDE_STAT 0xc0040090
#define PBA_BCDE_PBADR 0xc0040098
+#define PBA_BCDE_DR 0xc0040098
#define PBA_BCDE_OCIBAR 0xc00400a0
#define PBA_BCUE_CTL 0xc00400a8
#define PBA_BCUE_SET 0xc00400b0
#define PBA_BCUE_STAT 0xc00400b8
#define PBA_BCUE_PBADR 0xc00400c0
+#define PBA_BCUE_DR 0xc00400c0
#define PBA_BCUE_OCIBAR 0xc00400c8
#define PBA_PBOCRN(n) (PBA_PBOCR0 + ((PBA_PBOCR1 - PBA_PBOCR0) * (n)))
#define PBA_PBOCR0 0xc00400d0
@@ -71,41 +73,42 @@
#define PBA_XSHINCN(n) (PBA_XSHINC0 + ((PBA_XSHINC1 - PBA_XSHINC0) * (n)))
#define PBA_XSHINC0 0xc0040140
#define PBA_XSHINC1 0xc0040160
-#define PBA_PIB_BASE 0x68000
-#define PBA_FIR 0x00068000
-#define PBA_FIR_AND 0x00068001
-#define PBA_FIR_OR 0x00068002
-#define PBA_FIRMASK 0x00068003
-#define PBA_FIRMASK_AND 0x00068004
-#define PBA_FIRMASK_OR 0x00068005
-#define PBA_FIRACT0 0x00068006
-#define PBA_FIRACT1 0x00068007
-#define PBA_OCCACT 0x0006800a
-#define PBA_CFG 0x0006800b
-#define PBA_ERRRPT0 0x0006800c
-#define PBA_ERRRPT1 0x0006800d
-#define PBA_ERRRPT2 0x0006800e
+// The following are SCOM addresses, not OCI addresses
+#define PBA_PIB_BASE 0x05012840
+#define PBA_FIR 0x05012840
+#define PBA_FIR_AND 0x05012841
+#define PBA_FIR_OR 0x05012842
+#define PBA_FIRMASK 0x05012843
+#define PBA_FIRMASK_AND 0x05012844
+#define PBA_FIRMASK_OR 0x05012845
+#define PBA_FIRACT0 0x05012846
+#define PBA_FIRACT1 0x05012847
+#define PBA_OCCACT 0x0501284a
+#define PBA_CFG 0x0501284b
+#define PBA_ERRRPT0 0x0501284c
+#define PBA_ERRRPT1 0x0501284d
+#define PBA_ERRRPT2 0x0501284e
#define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n)))
-#define PBA_RBUFVAL0 0x00068010
-#define PBA_RBUFVAL1 0x00068011
-#define PBA_RBUFVAL2 0x00068012
-#define PBA_RBUFVAL3 0x00068013
-#define PBA_RBUFVAL4 0x00068014
-#define PBA_RBUFVAL5 0x00068015
+#define PBA_RBUFVAL0 0x05012850
+#define PBA_RBUFVAL1 0x05012851
+#define PBA_RBUFVAL2 0x05012852
+#define PBA_RBUFVAL3 0x05012853
+#define PBA_RBUFVAL4 0x05012854
+#define PBA_RBUFVAL5 0x05012855
#define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n)))
-#define PBA_WBUFVAL0 0x00068018
-#define PBA_WBUFVAL1 0x00068019
-#define PBA_TRUSTEDPIB_BASE 0x68020
+#define PBA_WBUFVAL0 0x05012858
+#define PBA_WBUFVAL1 0x05012859
+#define PBA_TRUSTEDPIB_BASE 0x05012B00
#define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n)))
-#define PBA_BAR0 0x00068020
-#define PBA_BAR1 0x00068021
-#define PBA_BAR2 0x00068022
-#define PBA_BAR3 0x00068023
+#define PBA_BAR0 0x05012b00
+#define PBA_BAR1 0x05012b01
+#define PBA_BAR2 0x05012b02
+#define PBA_BAR3 0x05012b03
#define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n)))
-#define PBA_BARMSK0 0x00068024
-#define PBA_BARMSK1 0x00068025
-#define PBA_BARMSK2 0x00068026
-#define PBA_BARMSK3 0x00068027
+#define PBA_BARMSK0 0x05012b04
+#define PBA_BARMSK1 0x05012b05
+#define PBA_BARMSK2 0x05012b06
+#define PBA_BARMSK3 0x05012b07
#endif // __PBA_REGISTER_ADDRESSES_H__
diff --git a/src/lib/ppc405lib/chip_config.h b/src/lib/ppc405lib/chip_config.h
index 7e495de..f4a3b41 100644
--- a/src/lib/ppc405lib/chip_config.h
+++ b/src/lib/ppc405lib/chip_config.h
@@ -86,18 +86,4 @@ left_justify_centaur_config(ChipConfig config)
#endif // __ASSEMBLER__
-
-#define CHIP_CONFIG_CORE_BASE 0
-#define CHIP_CONFIG_CORE(n) \
- ((0x8000000000000000ull >> CHIP_CONFIG_CORE_BASE) >> (n))
-
-#define CHIP_CONFIG_MCS_BASE 16
-#define CHIP_CONFIG_MCS(n) \
- ((0x8000000000000000ull >> CHIP_CONFIG_MCS_BASE) >> (n))
-
-#define CHIP_CONFIG_CENTAUR_BASE 24
-#define CHIP_CONFIG_CENTAUR(n) \
- ((0x8000000000000000ull >> CHIP_CONFIG_CENTAUR_BASE) >> (n))
-
-
#endif /* __CHIP_CONFIG_H__ */
diff --git a/src/occ_405/amec/amec_sensors_centaur.c b/src/occ_405/amec/amec_sensors_centaur.c
index 8cd50c3..f4327ea 100644
--- a/src/occ_405/amec/amec_sensors_centaur.c
+++ b/src/occ_405/amec/amec_sensors_centaur.c
@@ -43,6 +43,7 @@
#include "sensor_enum.h"
#include "amec_service_codes.h"
#include <amec_sensors_centaur.h>
+#include "centaur_mem_data.h"
/******************************************************************************/
/* Globals */
@@ -57,12 +58,9 @@ extern uint8_t G_centaur_nest_lfir6;
/******************************************************************************/
/* Forward Declarations */
/******************************************************************************/
-/* TODO - RTC 163359 Centaur support */
-#if 0
-void amec_update_dimm_dts_sensors(MemData * i_sensor_cache, uint8_t i_centaur);
-void amec_update_centaur_dts_sensors(MemData * i_sensor_cache, uint8_t i_centaur);
-void amec_perfcount_getmc( MemData * i_sensor_cache, uint8_t i_centaur);
-#endif
+void amec_update_dimm_dts_sensors(CentaurMemData * i_sensor_cache, uint8_t i_centaur);
+void amec_update_centaur_dts_sensors(CentaurMemData * i_sensor_cache, uint8_t i_centaur);
+void amec_perfcount_getmc( CentaurMemData * i_sensor_cache, uint8_t i_centaur);
/******************************************************************************/
/* Code */
@@ -80,11 +78,9 @@ void amec_perfcount_getmc( MemData * i_sensor_cache, uint8_t i_centaur);
// End Function Specification
void amec_update_centaur_sensors(uint8_t i_centaur)
{
-/* TODO - RTC 163359 Centaur support */
-#if 0
if(CENTAUR_PRESENT(i_centaur))
{
- MemData * l_sensor_cache = cent_get_centaur_data_ptr(i_centaur);
+ CentaurMemData * l_sensor_cache = cent_get_centaur_data_ptr(i_centaur);
if(CENTAUR_UPDATED(i_centaur))
{
amec_update_dimm_dts_sensors(l_sensor_cache, i_centaur);
@@ -93,7 +89,6 @@ void amec_update_centaur_sensors(uint8_t i_centaur)
amec_perfcount_getmc(l_sensor_cache, i_centaur);
CLEAR_CENTAUR_UPDATED(i_centaur);
}
-#endif
}
// Function Specification
@@ -106,9 +101,7 @@ void amec_update_centaur_sensors(uint8_t i_centaur)
// Thread: RealTime Loop
//
// End Function Specification
-/* TODO - RTC 163359 Centaur support */
-#if 0
-void amec_update_dimm_dts_sensors(MemData * i_sensor_cache, uint8_t i_centaur)
+void amec_update_dimm_dts_sensors(CentaurMemData * i_sensor_cache, uint8_t i_centaur)
{
#define MIN_VALID_DIMM_TEMP 1
#define MAX_VALID_DIMM_TEMP 125 //according to Mike Pardiek
@@ -246,20 +239,17 @@ void amec_update_dimm_dts_sensors(MemData * i_sensor_cache, uint8_t i_centaur)
L_ran_once[i_centaur] = TRUE;
AMEC_DBG("Centaur[%d]: HotDimm=%d\n",i_centaur,l_hottest_dimm_temp);
}
-#endif
// Function Specification
//
// Name: amec_update_centaur_dts_sensors
//
-// Description: Updates sensors taht have data grabbed by the fast core data
+// Description: Updates sensors that have data grabbed by the fast core data
//
// Thread: RealTime Loop
//
// End Function Specification
-/* TODO - RTC 163359 Centaur support */
-#if 0
-void amec_update_centaur_dts_sensors(MemData * i_sensor_cache, uint8_t i_centaur)
+void amec_update_centaur_dts_sensors(CentaurMemData * i_sensor_cache, uint8_t i_centaur)
{
#define MIN_VALID_CENT_TEMP 1
#define MAX_VALID_CENT_TEMP 125 //according to Mike Pardiek
@@ -377,7 +367,6 @@ void amec_update_centaur_dts_sensors(MemData * i_sensor_cache, uint8_t i_centaur
AMEC_DBG("Centaur[%d]: HotCentaur=%d\n",i_centaur,l_dts);
}
-#endif
// Function Specification
//
@@ -393,7 +382,7 @@ void amec_update_centaur_temp_sensors(void)
uint32_t k, l_hot;
// -----------------------------------------------------------
- // Find hottest temperature from all centaurs for this P8 chip
+ // Find hottest temperature from all centaurs for this Proc chip
// -----------------------------------------------------------
for(l_hot = 0, k=0; k < MAX_NUM_CENTAURS; k++)
{
@@ -406,7 +395,7 @@ void amec_update_centaur_temp_sensors(void)
AMEC_DBG("HotCentaur=%d\n",l_hot);
// --------------------------------------------------------
- // Find hottest temperature from all DIMMs for this P8 chip
+ // Find hottest temperature from all DIMMs for this Proc chip
// --------------------------------------------------------
for(l_hot = 0, k=0; k < MAX_NUM_CENTAURS; k++)
{
@@ -430,9 +419,8 @@ void amec_update_centaur_temp_sensors(void)
// Thread: RealTime Loop
//
// End Function Specification
-/* TODO - RTC 163359 Centaur support */
-#if 0
-void amec_perfcount_getmc( MemData * i_sensor_cache,
+
+void amec_perfcount_getmc( CentaurMemData * i_sensor_cache,
uint8_t i_centaur)
{
/*------------------------------------------------------------------------*/
@@ -452,7 +440,7 @@ void amec_perfcount_getmc( MemData * i_sensor_cache,
/* Code */
/*------------------------------------------------------------------------*/
- MemData * l_sensor_cache = i_sensor_cache;
+ CentaurMemData * l_sensor_cache = i_sensor_cache;
for(i_mc_id=0; i_mc_id<2; i_mc_id++)
{
@@ -682,18 +670,17 @@ void amec_perfcount_getmc( MemData * i_sensor_cache,
// ------------------------------------------------------------
tempreg = g_amec->proc[0].memctl[i_centaur].centaur.portpair[0].perf.memread2ms;
tempreg += g_amec->proc[0].memctl[i_centaur].centaur.portpair[1].perf.memread2ms;
- sensor_update( (&(g_amec->proc[0].memctl[i_centaur].mrd2ms)), tempreg);
+ sensor_update( (&(g_amec->proc[0].memctl[i_centaur].mrd)), tempreg);
// -------------------------------------------------------------
// Sensor: MWRMx (0.01 Mrps) Memory write requests per sec
// -------------------------------------------------------------
tempreg = g_amec->proc[0].memctl[i_centaur].centaur.portpair[0].perf.memwrite2ms;
tempreg += g_amec->proc[0].memctl[i_centaur].centaur.portpair[1].perf.memwrite2ms;
- sensor_update( (&(g_amec->proc[0].memctl[i_centaur].mwr2ms)), tempreg);
+ sensor_update( (&(g_amec->proc[0].memctl[i_centaur].mwr)), tempreg);
return;
}
-#endif
/*----------------------------------------------------------------------------*/
/* End */
diff --git a/src/occ_405/amec/amec_slave_smh.c b/src/occ_405/amec/amec_slave_smh.c
index 0536ee6..703c9a2 100755
--- a/src/occ_405/amec/amec_slave_smh.c
+++ b/src/occ_405/amec/amec_slave_smh.c
@@ -429,8 +429,12 @@ void amec_slv_common_tasks_post(void)
// Call amec_power_control
amec_power_control();
- // Apply memory power control, if needed.
- amec_mem_power_control();
+ if (MEM_TYPE_CUMULUS != G_sysConfigData.mem_type)
+ {
+ // Nimbus only
+ // Apply memory power control, if needed.
+ amec_mem_power_control();
+ }
// Call the OCC slave's processor voting box
amec_slv_proc_voting_box();
@@ -488,12 +492,11 @@ void amec_slv_state_0(void)
{
AMEC_DBG("\tAMEC Slave State 0\n");
-/* Not yet supported TODO Centaur support RTC 163359
//-------------------------------------------------------
// Update Centaur sensors (for this tick)
//-------------------------------------------------------
amec_update_centaur_sensors(CENTAUR_0);
-*/
+
//-------------------------------------------------------
// Update vector sensors
//-------------------------------------------------------
@@ -522,7 +525,6 @@ void amec_slv_state_1(void)
{
AMEC_DBG("\tAMEC Slave State 1\n");
-/* Not yet supported TODO Centaur support RTC 163359
//-------------------------------------------------------
// Update Centaur sensors (for this tick)
//-------------------------------------------------------
@@ -532,7 +534,6 @@ void amec_slv_state_1(void)
// Update Proc Level Centaur/DIMM Temperature sensors
//-------------------------------------------------------
amec_update_centaur_temp_sensors();
-*/
}
@@ -547,12 +548,10 @@ void amec_slv_state_2(void)
{
AMEC_DBG("\tAMEC Slave State 2\n");
-/* Not yet supported TODO Centaur support RTC 163359
//-------------------------------------------------------
// Update Centaur sensors (for this tick)
//-------------------------------------------------------
amec_update_centaur_sensors(CENTAUR_2);
-*/
// Call VRM Vdd thermal controller
amec_controller_vrm_vdd_thermal();
@@ -575,9 +574,7 @@ void amec_slv_state_3(void)
//-------------------------------------------------------
// Update Centaur sensors (for this tick)
//-------------------------------------------------------
-/* Not yet supported TODO Centaur support RTC 163359
amec_update_centaur_sensors(CENTAUR_3);
-*/
//-------------------------------------------------------
// Perform amec_analytics (set amec_analytics_slot to 3)
@@ -601,12 +598,10 @@ void amec_slv_state_4(void)
{
AMEC_DBG("\tAMEC Slave State 4\n");
-/* Not yet supported TODO Centaur support RTC 163359
//-------------------------------------------------------
// Update Centaur sensors (for this tick)
//-------------------------------------------------------
amec_update_centaur_sensors(CENTAUR_4);
-*/
//-------------------------------------------------------
// Run WOF Algorithm
@@ -629,9 +624,9 @@ void amec_slv_state_5(void)
AMEC_DBG("\tAMEC Slave State 5\n");
//-------------------------------------------------------
- // Update Centaur sensors (for this tick) TODO Centaur support RTC 163359
+ // Update Centaur sensors (for this tick)
//-------------------------------------------------------
-// amec_update_centaur_sensors(CENTAUR_5);
+ amec_update_centaur_sensors(CENTAUR_5);
//-------------------------------------------------------
// Update partition sensors for DPS algorithms (for this tick)
@@ -654,12 +649,10 @@ void amec_slv_state_6(void)
{
AMEC_DBG("\tAMEC Slave State 6\n");
-/* Not yet supported TODO Centaur support RTC 163359
//-------------------------------------------------------
// Update Centaur sensors (for this tick)
//-------------------------------------------------------
amec_update_centaur_sensors(CENTAUR_6);
-*/
}
@@ -674,12 +667,10 @@ void amec_slv_state_7(void)
{
AMEC_DBG("\tAMEC Slave State 7\n");
-/* Not yet supported TODO Centaur support RTC 163359
//-------------------------------------------------------
// Update Centaur sensors (for this tick)
//-------------------------------------------------------
amec_update_centaur_sensors(CENTAUR_7);
-*/
}
// Function Specification
@@ -1313,9 +1304,11 @@ void amec_slv_substate_7_0(void)
// Call memory thermal controller based on DIMM temperature
amec_controller_dimm_thermal();
- // Call memory thermal controller based on Centaur temperature
- // TODO: RTC 163359 - OCC Centaur Support
- //amec_controller_centaur_thermal();
+ if (MEM_TYPE_CUMULUS == G_sysConfigData.mem_type)
+ {
+ // Call memory thermal controller based on Centaur temperature
+ amec_controller_centaur_thermal();
+ }
}
diff --git a/src/occ_405/cent/centaur_control.c b/src/occ_405/cent/centaur_control.c
index 1edb295..534aa9e 100755
--- a/src/occ_405/cent/centaur_control.c
+++ b/src/occ_405/cent/centaur_control.c
@@ -39,9 +39,9 @@
#include "rtls.h"
#include "apss.h"
#include "state.h"
-//#include "gpe_scom.h"
-//#include "centaur_firmware_registers.h"
-//#include "centaur_register_addresses.h"
+#include "centaur_structs.h"
+#include "centaur_firmware_registers.h"
+#include "centaur_register_addresses.h"
#include "amec_sys.h"
#include "memory.h"
@@ -78,9 +78,10 @@ typedef enum
//Pore flex request for the GPE job that is used for centaur init.
GpeRequest G_centaur_control_request;
-//TODO: RTC 163359 - not ready yet for centaur control data structures
-//GPE_BUFFER(GpeScomParms G_centaur_control_reg_parms);
-//GPE_BUFFER(scomList_t G_centaurThrottle[NUM_CENT_THROTTLE_SCOMS]);
+// @see CentaurScomParms in centaur_structs.h
+GPE_BUFFER(CentaurScomParms_t G_centaur_control_reg_parms);
+// scomList_t @see centaur_configuration.h
+GPE_BUFFER(scomList_t G_centaurThrottle[NUM_CENT_THROTTLE_SCOMS]);
//bitmap of configured MBA's (2 per centaur, lsb is centaur 0/mba 0)
//same variable used for tracking bit maps of rdimms (4 per mc, 2 mc pairs)
@@ -133,8 +134,6 @@ uint16_t centaurThrottle_convert2Numerator(uint16_t i_throttle, uint8_t i_cent,
return (uint16_t)l_nvalue;
}
-#if 0 // TODO: 163359 - Not Ready yet for centaur control
-
//////////////////////////
// Function Specification
//
@@ -235,15 +234,18 @@ void cent_update_nlimits(uint32_t i_cent)
// Name: centaur_control
//
// Description: Performs centaur control.
+// return TRUE settings changed HW needs to be updated.
+// return FALSE settings did not change
//
// End Function Specification
-void centaur_control( task_t* i_task )
+bool centaur_control( memory_control_task_t * i_memControlTask )
{
- amec_centaur_t *l_cent_ptr = NULL;
+ bool throttle_updated = TRUE;
+ amec_centaur_t *l_cent_ptr = NULL;
+ int l_cent = i_memControlTask->curMemIndex;
- // Pointer to parameter field for GPE request
- GpeScomParms * l_parms =
- (GpeScomParms *)(l_centControlTask->gpe_req.parameter);
+ CentaurScomParms_t * l_parms =
+ (CentaurScomParms_t *)(i_memControlTask->gpe_req.cmd_data);
do
{
@@ -278,15 +280,10 @@ void centaur_control( task_t* i_task )
( l_mba23_speed.word32 == l_cent_ptr->portpair[1].last_mem_speed_sent.word32 )
)
{
+ throttle_updated = FALSE;
break;
}
- //TRAC_INFO("task_centaur_control: New centaur[%d] throttle values mba01[0x%08x], mba23[0x%08x], throt[%d] ",
- // l_cent,
- // l_mba01_speed.word32,
- // l_mba23_speed.word32,
- // g_amec->mem_speed_request);
-
/// Set up Centuar Scom Registers - array of Scoms
/// [0]: N/M Throttle MBA01
/// [1]: N/M Throttle MBA23
@@ -296,7 +293,7 @@ void centaur_control( task_t* i_task )
if(MBA_CONFIGURED(l_cent, 0))
{
/// [0]: Set up N/M throttle MBA01
- G_centaurThrottle[NM_THROTTLE_MBA01].commandType = GPE_SCOM_RMW;
+ G_centaurThrottle[NM_THROTTLE_MBA01].commandType = CENTAUR_SCOM_RMW;
G_centaurThrottle[NM_THROTTLE_MBA01].instanceNumber = l_cent;
// Set up value to be written
l_mbafarbq.fields.cfg_nm_n_per_mba = l_mba01_n_per_mba;
@@ -305,14 +302,14 @@ void centaur_control( task_t* i_task )
}
else
{
- G_centaurThrottle[NM_THROTTLE_MBA01].commandType = GPE_SCOM_NOP;
+ G_centaurThrottle[NM_THROTTLE_MBA01].commandType = CENTAUR_SCOM_NOP;
}
//only write to MBA23 if configured
if(MBA_CONFIGURED(l_cent, 1))
{
/// [1]: Set up N/M throttle MBA23
- G_centaurThrottle[NM_THROTTLE_MBA23].commandType = GPE_SCOM_RMW;
+ G_centaurThrottle[NM_THROTTLE_MBA23].commandType = CENTAUR_SCOM_RMW;
G_centaurThrottle[NM_THROTTLE_MBA23].instanceNumber = l_cent;
// Set up value to be written
l_mbafarbq.fields.cfg_nm_n_per_mba = l_mba23_n_per_mba;
@@ -321,7 +318,7 @@ void centaur_control( task_t* i_task )
}
else
{
- G_centaurThrottle[NM_THROTTLE_MBA23].commandType = GPE_SCOM_NOP;
+ G_centaurThrottle[NM_THROTTLE_MBA23].commandType = CENTAUR_SCOM_NOP;
}
@@ -330,17 +327,15 @@ void centaur_control( task_t* i_task )
/// 0:7 select mask of MCS units
/// 8:15 select the sync type (12 = N/M throttle)
/// 57:63 must be zeros to address DW0 in cacheline
- //G_centaurThrottle[MBS_THROTTLE_SYNC].commandType = GPE_SCOM_NOP;
- G_centaurThrottle[MBS_THROTTLE_SYNC].commandType = GPE_SCOM_CENTAUR_SYNC_ALL;
+ //G_centaurThrottle[MBS_THROTTLE_SYNC].commandType = CENTAUR_SCOM_NOP;
+ G_centaurThrottle[MBS_THROTTLE_SYNC].commandType = CENTAUR_SCOM_CENTAUR_SYNC_ALL;
G_centaurThrottle[MBS_THROTTLE_SYNC].data = CENTAUR_RESET_N_M_THROTTLE_COUNTER_SYNC |
CENTAUR_MYSTERY_SYNC; //This is the "PC" sync bit
/// Set up GPE parameters
- l_parms->scomList = (uint32_t) (&G_centaurThrottle);
- l_parms->entries = 3;
- l_parms->options = 0;
- l_parms->rc = 0;
- l_parms->errorIndex = 0;
+ l_parms->scomList = G_centaurThrottle;
+ l_parms->entries = 2;
+ l_parms->error.ffdc = 0;
// Update the last sent throttle value, this will get
// cleared if the GPE does not complete successfully.
@@ -349,6 +344,7 @@ void centaur_control( task_t* i_task )
} while(0);
+ return throttle_updated;
}
@@ -391,21 +387,19 @@ void centaur_control_init( void )
G_centaurThrottle[NM_THROTTLE_MBA23].mask = l_mbafarbq.value;
// Set up GPE parameters
- G_centaur_control_reg_parms.rc = 0;
+ G_centaur_control_reg_parms.error.ffdc = 0;
G_centaur_control_reg_parms.entries = 0;
- G_centaur_control_reg_parms.scomList = (uint32_t) (&G_centaurThrottle[0]);
- G_centaur_control_reg_parms.options = 0;
- G_centaur_control_reg_parms.errorIndex = 0;
+ G_centaur_control_reg_parms.scomList = &G_centaurThrottle[0];
//--------------------------------------------------
- // Initializes PoreFlex for Centaur Control Task, but
+ // Initializes GPE Centaur Control Task, but
// doesn't actually run anything until RTL
//--------------------------------------------------
l_rc_gpe = gpe_request_create(
&G_memory_control_task.gpe_req, // gpe_req for the task
&G_async_gpe_queue1, // queue
- IPC_ST_CENTAUR_CONTROL_FUNCID, // Function ID
- (uint32_t) &G_centaur_control_reg_parms, // parm for the task
+ IPC_ST_CENTAUR_SCOM_FUNCID, // Function ID
+ &G_centaur_control_reg_parms, // parm for the task
SSX_WAIT_FOREVER, //
NULL, // callback
NULL, // callback argument
@@ -445,8 +439,8 @@ void centaur_control_init( void )
);
addUsrDtlsToErrl(l_err, //io_err
- (uint8_t *) &G_centaur_control_request.ffdc, //i_dataPtr,
- sizeof(PoreFfdc), //i_size
+ (uint8_t *) &G_centaur_control_request.ffdc, //i_dataPtr,
+ sizeof(GpeFfdc), //i_size
ERRL_USR_DTL_STRUCT_VERSION_1, //version
ERRL_USR_DTL_BINARY_DATA); //type
@@ -456,17 +450,19 @@ void centaur_control_init( void )
return;
}
-bool check_centaur_checkstop(uint8_t cent)
+bool check_centaur_checkstop(memory_control_task_t * i_memControlTask )
{
+ errlHndl_t l_err = NULL;
+ int cent = i_memControlTask->curMemIndex;
// Check if the centaur has a channel checkstop. If it does,
// then do not log any errors. We also don't want to throttle
// a centaur that is in this condition.
- if(!(cent_chan_checkstop(cent)))
+ if(G_centaur_control_reg_parms.error.rc != CENTAUR_CHANNEL_CHECKSTOP)
{
- TRAC_ERR("task_memory_control: gpe_scom_centaur failed. "
+ TRAC_ERR("task_memory_control: IPC_ST_CENTAUR_SCOM failed. "
"cent=%d rc=%x, index=0x%08x",
- cent, G_centaur_control_reg_parms.rc,
- G_centaur_control_reg_parms.errorIndex);
+ cent, G_centaur_control_reg_parms.error.rc,
+ G_centaur_control_reg_parms.error.addr);
/* @
* @errortype
@@ -484,20 +480,20 @@ bool check_centaur_checkstop(uint8_t cent)
ERRL_SEV_PREDICTIVE, // Severity
NULL, // Trace Buf
DEFAULT_TRACE_SIZE, // Trace Size
- G_centaur_control_reg_parms.rc, // userdata1
- G_centaur_control_reg_parms.errorIndex // userdata2
+ G_centaur_control_reg_parms.error.rc, // userdata1
+ G_centaur_control_reg_parms.error.addr // userdata2
);
addUsrDtlsToErrl(l_err, //io_err
- (uint8_t *) &(memControlTask->gpe_req.ffdc), //i_dataPtr,
- sizeof(PoreFfdc), //i_size
- ERRL_USR_DTL_STRUCT_VERSION_1, //version
- ERRL_USR_DTL_BINARY_DATA); //type
+ (uint8_t *) &(i_memControlTask->gpe_req.ffdc), //i_dataPtr,
+ sizeof(GpeFfdc), //i_size
+ ERRL_USR_DTL_STRUCT_VERSION_1, //version
+ ERRL_USR_DTL_BINARY_DATA); //type
//callout the centaur
addCalloutToErrl(l_err,
ERRL_CALLOUT_TYPE_HUID,
- G_sysConfigData.centaur_huids[memIndex],
+ G_sysConfigData.centaur_huids[cent],
ERRL_CALLOUT_PRIORITY_MED);
//callout the processor
@@ -515,5 +511,3 @@ bool check_centaur_checkstop(uint8_t cent)
}
-#endif // TODO: RTC 163359 - Not Ready yet for centaur control
-
diff --git a/src/occ_405/cent/centaur_control.h b/src/occ_405/cent/centaur_control.h
index afc766e..b6bb817 100755
--- a/src/occ_405/cent/centaur_control.h
+++ b/src/occ_405/cent/centaur_control.h
@@ -60,12 +60,13 @@ extern memory_control_task_t G_memory_control_task;
//*************************************************************************
//Collect centaur data for all centaur in specified range
-void centaur_control( task_t* i_task );
+//void centaur_control( task_t* i_task );
+bool centaur_control( memory_control_task_t * i_memControlTask );
//Initialize structures for collecting centaur data.
//void centaur_control_init( void ) INIT_SECTION;
void centaur_control_init( void );
-bool check_centaur_checkstop(uint8_t cent);
+bool check_centaur_checkstop( memory_control_task_t * i_memControlTask );
#endif //_CENTAUR_CONTROL_H
diff --git a/src/occ_405/cent/centaur_data.c b/src/occ_405/cent/centaur_data.c
index 98636f2..4228c03 100755
--- a/src/occ_405/cent/centaur_data.c
+++ b/src/occ_405/cent/centaur_data.c
@@ -38,8 +38,10 @@
#include "apss.h"
#include "state.h"
#include "occhw_scom.h"
-//#include "centaur_firmware_registers.h"
-//#include "centaur_register_addresses.h"
+#include "centaur_structs.h"
+#include "centaur_mem_data.h"
+#include "centaur_firmware_registers.h"
+#include "centaur_register_addresses.h"
//*************************************************************************/
// Externs
@@ -90,36 +92,49 @@ typedef enum
// Globals
//*************************************************************************/
-/* TODO 163359: PORE/MemData issues */
-#if 0
+/**
+ * GPE shared data area for gpe0 tracebuffer and size
+ */
+extern gpe_shared_data_t G_shared_gpe_data;
+
+//Notes MemData is defined @
+// /afs/awd/proj/p9/eclipz/KnowledgeBase/eclipz/chips/p8/working/procedures/lib/gpe_data.h
+// struct {
+// MemDataMcs mcs; // not used
+// MemDataSensorCache scache;
+// } MemData;
//Global array of centaur data buffers
-GPE_BUFFER(MemData G_centaur_data[NUM_CENTAUR_DATA_BUFF +
+GPE_BUFFER(CentaurMemData G_centaur_data[NUM_CENTAUR_DATA_BUFF +
NUM_CENTAUR_DOUBLE_BUF +
NUM_CENTAUR_DATA_EMPTY_BUF]);
//pore request for scoming centaur registers
-PoreFlex G_cent_scom_req;
+GpeRequest G_cent_scom_req; // p8/working/procedures/ssx/pgp/pgp_async.h
-//input/output parameters for gpe_scom_centaur()
-GPE_BUFFER(GpeScomParms G_cent_scom_gpe_parms);
+//input/output parameters for IPC_ST_CENTAUR_SCOM()
+GPE_BUFFER(CentaurScomParms_t G_cent_scom_gpe_parms);
//scom command list entry
GPE_BUFFER(scomList_t G_cent_scom_list_entry[NUM_CENT_OPS]);
-//buffer for storing output from running gpe_scom_centaur()
+//buffer for storing output from running IPC_ST_CENTAUR_SCOM()
GPE_BUFFER(uint64_t G_cent_scom_data[MAX_NUM_CENTAURS]) = {0};
+// parms for call to IPC_ST_CENTAUR_INIT_FUNCID
+GPE_BUFFER(CentaurConfigParms_t G_gpe_centaur_config_args);
+
+GPE_BUFFER(CentaurConfiguration_t G_centaurConfiguration);
//Global array of centaur data pointers
-MemData * G_centaur_data_ptrs[MAX_NUM_CENTAURS] = { &G_centaur_data[0],
+CentaurMemData * G_centaur_data_ptrs[MAX_NUM_CENTAURS] = { &G_centaur_data[0],
&G_centaur_data[1], &G_centaur_data[2], &G_centaur_data[3],
&G_centaur_data[4], &G_centaur_data[5], &G_centaur_data[6],
&G_centaur_data[7]};
//Global structures for gpe get mem data parms
-GPE_BUFFER(GpeGetMemDataParms G_centaur_data_parms);
+GPE_BUFFER(CentaurGetMemDataParms_t G_centaur_data_parms);
//Pore flex request for the GPE job that is used for centaur init.
-PoreFlex G_centaur_reg_pore_req;
+GpeRequest G_centaur_reg_gpe_req;
//Centaur structures used for task data pointers.
centaur_data_task_t G_centaur_data_task = {
@@ -127,9 +142,9 @@ centaur_data_task_t G_centaur_data_task = {
.current_centaur = 0,
.end_centaur = 7,
.prev_centaur = 7,
- .centaur_data_ptr = &G_centaur_data[8]
+ .centaur_data_ptr = &G_centaur_data[MAX_NUM_CENTAURS]
};
-#endif
+
dimm_sensor_flags_t G_dimm_enabled_sensors = {0};
dimm_sensor_flags_t G_dimm_present_sensors = {0};
@@ -177,67 +192,10 @@ uint8_t G_centaur_nest_lfir6 = 0;
//number of SC polls to wait between i2c recovery attempts
#define CENT_SC_MAX_INTERVAL 256
-/* TODO: RTC 163359 - Reenable when needed */
-#if 0
//determine scom address of MCIFIR register for given Centaur n
#define MCS0_MCIFIR_N(n) \
( (n<4)? (MCS0_MCIFIR + ((MCS1_MCIFIR - MCS0_MCIFIR) * (n))) : (MCS4_MCIFIR + ((MCS5_MCIFIR - MCS4_MCIFIR) * (n-4))) )
-#endif
-
-//mask for channel checkstop
-#define MCIFIR_CHAN_CKSTOP_MASK 0x0000000100000000
-
-/* TODO: RTC 163359 - Reenable when needed */
-#if 0
-bool cent_chan_checkstop(const uint8_t i_cent)
-{
- uint32_t l_scom_addr = 0;
- bool l_rc = FALSE;
- uint64_t l_data;
- int l_scom_rc = 0;
-
- // TODO: RTC 163359 Centaur support
- // We are unable to SCOM from the 405, so this scom was removed.
- // Will need to determine how to get this information in the future.
-
- if(!l_scom_rc)
- {
- //check for channel checkstop (bit 31)
- if(l_data & MCIFIR_CHAN_CKSTOP_MASK)
- {
- l_rc = TRUE;
-
- if(CENTAUR_PRESENT(i_cent))
- {
- //remove checkstopped centaur from presence bitmap
- G_present_centaurs &= ~(CENTAUR_BY_MASK(i_cent));
-
- //remove the dimm temperature sensors behind this centaur from presence bitmap
- G_dimm_enabled_sensors.bytes[i_cent] = 0x00;
- TRAC_IMP("Channel checkstop detected on Centaur[%d] scom_addr[0x%08X] G_present_centaurs[0x%08X]",
- i_cent,
- l_scom_addr,
- G_present_centaurs);
-
- TRAC_IMP("Updated bitmap of enabled dimm temperature sensors: 0x%08X %08X",
- G_dimm_enabled_sensors.words[0],
- G_dimm_enabled_sensors.words[1]);
- }
- }
- }
- else
- {
- TRAC_ERR("cent_chan_checkstop: Error accessing MCIFIR register for Centaur[%d] scom_addr[0x%08X]",
- i_cent,
- l_scom_addr);
- }
- return l_rc;
-}
-#endif // #if 0
-
-/* TODO: RTC 163359 - Reenable when needed */
-#if 0
void cent_recovery(uint32_t i_cent)
{
int l_rc = 0;
@@ -293,22 +251,23 @@ void cent_recovery(uint32_t i_cent)
//Check for failure and log an error if we haven't already logged one for this centaur
//but keep retrying.
if(L_gpe_scheduled &&
- (!async_request_completed(&G_cent_scom_req.request) || G_cent_scom_gpe_parms.rc) &&
+ (!async_request_completed(&G_cent_scom_req.request) ||
+ G_cent_scom_gpe_parms.error.rc) &&
(!(L_cent_callouts & l_cent_mask)))
{
// Check if the centaur has a channel checkstop. If it does, then do not
// log any errors
- if(!(cent_chan_checkstop(l_prev_cent)))
+ if(G_cent_scom_gpe_parms.error.rc != CENTAUR_CHANNEL_CHECKSTOP)
{
//Mark the centaur as being called out
L_cent_callouts |= l_cent_mask;
// There was an error doing the recovery scoms
- TRAC_ERR("cent_recovery: gpe_scom_centaur failed. rc[0x%08x] cent[%d] entries[%d] errorIndex[0x%08X]",
- G_cent_scom_gpe_parms.rc,
+ TRAC_ERR("cent_recovery: IPC_ST_CENTAUR_SCOM failed. rc[0x%08x] cent[%d] entries[%d] errorIndex[0x%08X]",
+ G_cent_scom_gpe_parms.error.rc,
l_prev_cent,
G_cent_scom_gpe_parms.entries,
- G_cent_scom_gpe_parms.errorIndex);
+ G_cent_scom_gpe_parms.error.addr);
/* @
* @errortype
@@ -326,14 +285,14 @@ void cent_recovery(uint32_t i_cent)
ERRL_SEV_PREDICTIVE, //Severity
NULL, //Trace Buf
DEFAULT_TRACE_SIZE, //Trace Size
- G_cent_scom_gpe_parms.rc, //userdata1
- G_cent_scom_gpe_parms.errorIndex //userdata2
+ G_cent_scom_gpe_parms.error.rc, //userdata1
+ G_cent_scom_gpe_parms.error.addr //userdata2
);
//dump ffdc contents collected by ssx
addUsrDtlsToErrl(l_err, //io_err
(uint8_t *) &(G_cent_scom_req.ffdc), //i_dataPtr,
- sizeof(PoreFfdc), //i_size
+ sizeof(GpeFfdc), //i_size
ERRL_USR_DTL_STRUCT_VERSION_1, //version
ERRL_USR_DTL_BINARY_DATA); //type
@@ -467,17 +426,17 @@ void cent_recovery(uint32_t i_cent)
//check if this centaur requires lfir6 recovery
if(G_centaur_nest_lfir6 & l_cent_mask)
{
- //Set the command type from GPE_SCOM_NOP to GPE_SCOM_RMW
+ //Set the command type from CENTAUR_SCOM_NOP to CENTAUR_SCOM_RMW
//these entries will reset the centaur DTS FSM and clear LFIR 6
//if recovery worked, LFIR 6 should remain cleared.
- G_cent_scom_list_entry[RESET_DTS_FSM].commandType = GPE_SCOM_WRITE;
- G_cent_scom_list_entry[CLEAR_NEST_LFIR6].commandType = GPE_SCOM_WRITE;
+ G_cent_scom_list_entry[RESET_DTS_FSM].commandType = CENTAUR_SCOM_WRITE;
+ G_cent_scom_list_entry[CLEAR_NEST_LFIR6].commandType = CENTAUR_SCOM_WRITE;
}
else
{
//these ops aren't needed so disable them
- G_cent_scom_list_entry[RESET_DTS_FSM].commandType = GPE_SCOM_NOP;
- G_cent_scom_list_entry[CLEAR_NEST_LFIR6].commandType = GPE_SCOM_NOP;
+ G_cent_scom_list_entry[RESET_DTS_FSM].commandType = CENTAUR_SCOM_NOP;
+ G_cent_scom_list_entry[CLEAR_NEST_LFIR6].commandType = CENTAUR_SCOM_NOP;
}
//Decrement the delay counter for centaur i2c recovery
@@ -507,13 +466,13 @@ void cent_recovery(uint32_t i_cent)
//clear the request for i2c recovery here
G_centaur_needs_recovery &= ~l_cent_mask;
- //Set the command type from GPE_SCOM_NOP to GPE_SCOM_RMW
+ //Set the command type from CENTAUR_SCOM_NOP to CENTAUR_SCOM_RMW
//this entry will disable the centaur sensor cache and
//set a flag to finish the recovery in a later call of this
//function (cent_recovery for a given centaur is called every
//2 msec)
- G_cent_scom_list_entry[DISABLE_SC].commandType = GPE_SCOM_RMW;
- G_cent_scom_list_entry[ENABLE_SC].commandType = GPE_SCOM_NOP;
+ G_cent_scom_list_entry[DISABLE_SC].commandType = CENTAUR_SCOM_RMW;
+ G_cent_scom_list_entry[ENABLE_SC].commandType = CENTAUR_SCOM_NOP;
L_i2c_finish_recovery[i_cent] = TRUE;
}
}
@@ -533,8 +492,8 @@ void cent_recovery(uint32_t i_cent)
}
//these ops aren't needed so disable them
- G_cent_scom_list_entry[DISABLE_SC].commandType = GPE_SCOM_NOP;
- G_cent_scom_list_entry[ENABLE_SC].commandType = GPE_SCOM_NOP;
+ G_cent_scom_list_entry[DISABLE_SC].commandType = CENTAUR_SCOM_NOP;
+ G_cent_scom_list_entry[ENABLE_SC].commandType = CENTAUR_SCOM_NOP;
// Finish the i2c recovery if it was started for this centaur
if(L_i2c_finish_recovery[i_cent] == TRUE)
@@ -545,11 +504,11 @@ void cent_recovery(uint32_t i_cent)
//clear the finish_recovery flag for this centaur
L_i2c_finish_recovery[i_cent] = FALSE;
- //Set the command type from GPE_SCOM_NOP to GPE_SCOM_RMW
+ //Set the command type from CENTAUR_SCOM_NOP to CENTAUR_SCOM_RMW
//this entry will re-enable the centaur sensor cache
//which will also cause the i2c master to be reset
- G_cent_scom_list_entry[DISABLE_SC].commandType = GPE_SCOM_NOP;
- G_cent_scom_list_entry[ENABLE_SC].commandType = GPE_SCOM_RMW;
+ G_cent_scom_list_entry[DISABLE_SC].commandType = CENTAUR_SCOM_NOP;
+ G_cent_scom_list_entry[ENABLE_SC].commandType = CENTAUR_SCOM_RMW;
}
}
@@ -564,17 +523,15 @@ void cent_recovery(uint32_t i_cent)
G_cent_scom_list_entry[READ_SCAC_LFIR].instanceNumber = i_cent;
// Set up GPE parameters
- G_cent_scom_gpe_parms.rc = 0;
+ G_cent_scom_gpe_parms.error.ffdc = 0;
G_cent_scom_gpe_parms.entries = NUM_CENT_OPS;
- G_cent_scom_gpe_parms.scomList = (uint32_t) (&G_cent_scom_list_entry[0]);
- G_cent_scom_gpe_parms.options = 0;
- G_cent_scom_gpe_parms.errorIndex = 0;
+ G_cent_scom_gpe_parms.scomList = &G_cent_scom_list_entry[0];
- // Submit Pore GPE without blocking
- l_rc = pore_flex_schedule(&G_cent_scom_req);
+ // Submit GPE request without blocking
+ l_rc = gpe_request_schedule(&G_cent_scom_req);
if(l_rc)
{
- TRAC_ERR("cent_recovery: pore_flex_schedule failed. rc = 0x%08x", l_rc);
+ TRAC_ERR("cent_recovery: gpe_request_schedule failed. rc = 0x%08x", l_rc);
/* @
* @errortype
* @moduleid CENT_RECOVERY_MOD
@@ -602,7 +559,6 @@ void cent_recovery(uint32_t i_cent)
}while(0);
}
-#endif // #if 0
// Function Specification
//
@@ -612,15 +568,14 @@ void cent_recovery(uint32_t i_cent)
// collection
//
// End Function Specification
-/* TODO: RTC 163359 - Reenable when needed */
-#if 0
-void task_centaur_data( task_t * i_task )
+void centaur_data( void )
{
errlHndl_t l_err = NULL; // Error handler
int rc = 0; // Return code
- MemData * l_temp = NULL;
- centaur_data_task_t * l_centaur_data_ptr = (centaur_data_task_t *)i_task->data_ptr;
- GpeGetMemDataParms * l_parms = (GpeGetMemDataParms *)(l_centaur_data_ptr->gpe_req.parameter);
+ CentaurMemData * l_temp = NULL;
+ centaur_data_task_t * l_centaur_data_ptr = &G_centaur_data_task;
+ CentaurGetMemDataParms_t * l_parms =
+ (CentaurGetMemDataParms_t *)(l_centaur_data_ptr->gpe_req.cmd_data);
static bool L_gpe_scheduled = FALSE;
static bool L_gpe_error_logged = FALSE;
static bool L_gpe_had_1_tick = FALSE;
@@ -684,11 +639,11 @@ void task_centaur_data( task_t * i_task )
{
//If the request is idle but not completed then there was an error
//(as long as the request was scheduled).
- if(!async_request_completed(&l_centaur_data_ptr->gpe_req.request) || l_parms->rc )
+ if(!async_request_completed(&l_centaur_data_ptr->gpe_req.request) || l_parms->error.rc )
{
// Check if the centaur has a channel checkstop. If it does, then do not
// log any errors
- if(!(cent_chan_checkstop(l_centaur_data_ptr->prev_centaur)))
+ if(G_cent_scom_gpe_parms.error.rc != CENTAUR_CHANNEL_CHECKSTOP)
{
//log an error the first time this happens but keep on running.
//eventually, we will timeout on the dimm & centaur temps not being updated
@@ -699,16 +654,15 @@ void task_centaur_data( task_t * i_task )
L_gpe_error_logged = TRUE;
// There was an error collecting the centaur sensor cache
- TRAC_ERR("task_centaur_data: gpe_get_mem_data failed. rc=0x%08x%08x, cur=%d, prev=%d",
- (uint32_t)(l_parms->rc >> 32),
- (uint32_t)(l_parms->rc),
+ TRAC_ERR("task_centaur_data: gpe_get_mem_data failed. rc=0x%08x, cur=%d, prev=%d",
+ l_parms->error.rc,
l_centaur_data_ptr->current_centaur,
l_centaur_data_ptr->prev_centaur);
/* @
* @errortype
* @moduleid CENT_TASK_DATA_MOD
* @reasoncode CENT_SCOM_ERROR
- * @userdata1 l_parms->rc
+ * @userdata1 l_parms->error.rc
* @userdata2 0
* @userdata4 OCC_NO_EXTENDED_RC
* @devdesc Failed to get centaur data
@@ -720,18 +674,18 @@ void task_centaur_data( task_t * i_task )
ERRL_SEV_PREDICTIVE, //Severity
NULL, //Trace Buf
DEFAULT_TRACE_SIZE, //Trace Size
- l_parms->rc, //userdata1
+ l_parms->error.rc, //userdata1
0 //userdata2
);
addUsrDtlsToErrl(l_err, //io_err
(uint8_t *) &(l_centaur_data_ptr->gpe_req.ffdc), //i_dataPtr,
- sizeof(PoreFfdc), //i_size
+ sizeof(GpeFfdc), //i_size
ERRL_USR_DTL_STRUCT_VERSION_1, //version
ERRL_USR_DTL_BINARY_DATA); //type
//Callouts depend on the return code of the gpe_get_mem_data procedure
- if(l_parms->rc == GPE_GET_MEM_DATA_DIED)
+ if(l_parms->error.rc == CENTAUR_GET_MEM_DATA_DIED)
{
//callout the processor
addCalloutToErrl(l_err,
@@ -739,7 +693,7 @@ void task_centaur_data( task_t * i_task )
G_sysConfigData.proc_huid,
ERRL_CALLOUT_PRIORITY_LOW);
}
- else if(l_parms->rc == GPE_GET_MEM_DATA_SENSOR_CACHE_FAILED)
+ else if(l_parms->error.rc == CENTAUR_GET_MEM_DATA_SENSOR_CACHE_FAILED)
{
//callout the previous centaur if present
if(CENTAUR_PRESENT(l_centaur_data_ptr->prev_centaur))
@@ -756,7 +710,7 @@ void task_centaur_data( task_t * i_task )
G_sysConfigData.proc_huid,
ERRL_CALLOUT_PRIORITY_LOW);
}
- else if(l_parms->rc == GPE_GET_MEM_DATA_UPDATE_FAILED)
+ else if(l_parms->error.rc == CENTAUR_GET_MEM_DATA_UPDATE_FAILED)
{
//callout the current centaur if present
if(CENTAUR_PRESENT(l_centaur_data_ptr->current_centaur))
@@ -868,16 +822,16 @@ void task_centaur_data( task_t * i_task )
l_parms->update = -1;
}
- l_parms->data = (uint32_t) l_centaur_data_ptr->centaur_data_ptr;
- l_parms->rc = 0;
+ l_parms->data = (uint64_t *)(l_centaur_data_ptr->centaur_data_ptr);
+ l_parms->error.ffdc = 0;
// Pore flex schedule gpe_get_mem_data
- // Check pore_flex_schedule return code if error
+ // Check gpe_request_schedule return code if error
// then request OCC reset.
- rc = pore_flex_schedule( &(l_centaur_data_ptr->gpe_req) );
+ rc = gpe_request_schedule( &(l_centaur_data_ptr->gpe_req) );
if(rc)
{
- TRAC_ERR("task_centaur_data: pore_flex_schedule failed for centaur data collection. rc=%d", rc);
+ TRAC_ERR("task_centaur_data: gpe_request_schedule failed for centaur data collection. rc=%d", rc);
/* @
* @errortype
* @moduleid CENT_TASK_DATA_MOD
@@ -895,12 +849,12 @@ void task_centaur_data( task_t * i_task )
NULL, //Trace Buf
DEFAULT_TRACE_SIZE, //Trace Size
rc, //userdata1
- l_parms->rc //userdata2
+ l_parms->error.rc //userdata2
);
addUsrDtlsToErrl(l_err, //io_err
(uint8_t *) &(l_centaur_data_ptr->gpe_req.ffdc), //i_dataPtr,
- sizeof(PoreFfdc), //i_size
+ sizeof(GpeFfdc), //i_size
ERRL_USR_DTL_STRUCT_VERSION_1, //version
ERRL_USR_DTL_BINARY_DATA); //type
@@ -911,16 +865,16 @@ void task_centaur_data( task_t * i_task )
L_gpe_scheduled = TRUE;
}
- } while(0);
+ }
+ while(0);
- //handle centaur i2c recovery requests and centaur workaround
+ //handle centaur i2c recovery requests and centaur workaround - Needed for P9??
if(CENTAUR_PRESENT(l_centaur_data_ptr->current_centaur))
{
cent_recovery(l_centaur_data_ptr->current_centaur);
}
return;
}
-#endif // #if 0
#define CENTAUR_SENSCACHE_ENABLE 0x020115CC
// Function Specification
@@ -930,8 +884,6 @@ void task_centaur_data( task_t * i_task )
// Description: Reads
//
// End Function Specification
-/* TODO: RTC 163359 - Reenable when needed */
-#if 0
int cent_get_enabled_sensors()
{
int l_rc = 0;
@@ -941,37 +893,36 @@ int cent_get_enabled_sensors()
{
// Set up scom list entry (there's only 1)
G_cent_scom_list_entry[0].scom = CENTAUR_SENSCACHE_ENABLE; //scom address
- G_cent_scom_list_entry[0].commandType = GPE_SCOM_READ_VECTOR; //scom operation to perform
+ G_cent_scom_list_entry[0].commandType = CENTAUR_SCOM_READ_VECTOR; //scom operation to perform
G_cent_scom_list_entry[0].instanceNumber = 0; //Ignored for READ_VECTOR operation
G_cent_scom_list_entry[0].pData = (uint64_t *) G_cent_scom_data; //scom data will be stored here
// Set up GPE parameters
- G_cent_scom_gpe_parms.rc = 0;
+ G_cent_scom_gpe_parms.error.ffdc = 0;
G_cent_scom_gpe_parms.entries = 1;
- G_cent_scom_gpe_parms.scomList = (uint32_t) (&G_cent_scom_list_entry[0]);
- G_cent_scom_gpe_parms.options = 0;
- G_cent_scom_gpe_parms.errorIndex = 0;
+ G_cent_scom_gpe_parms.scomList = &G_cent_scom_list_entry[0];
//Initializes PoreFlex
- l_rc = pore_flex_create( &G_cent_scom_req, // gpe_req for the task
- &G_pore_gpe1_queue, // queue
- gpe_scom_centaur, // entry point
- (uint32_t) &G_cent_scom_gpe_parms, // parm for the task
- SSX_SECONDS(2), // timeout
- NULL, // callback
- NULL, // callback argument
- ASYNC_REQUEST_BLOCKING ); // options
+ l_rc = gpe_request_create(
+ &G_cent_scom_req, // gpe_req for the task
+ &G_async_gpe_queue1, // queue
+ IPC_ST_CENTAUR_SCOM_FUNCID, // Function ID
+ &G_cent_scom_gpe_parms, // parm for the task
+ SSX_SECONDS(2), // timeout
+ NULL, // callback
+ NULL, // callback argument
+ ASYNC_REQUEST_BLOCKING ); // options
if(l_rc)
{
- TRAC_ERR("cent_get_enabled_sensors: pore_flex_create failed. rc = 0x%08x", l_rc);
+ TRAC_ERR("cent_get_enabled_sensors: gpe_request_create failed. rc = 0x%08x", l_rc);
break;
}
// Submit Pore GPE and wait for completion
- l_rc = pore_flex_schedule(&G_cent_scom_req);
+ l_rc = gpe_request_schedule(&G_cent_scom_req);
if(l_rc)
{
- TRAC_ERR("cent_get_enabled_sensors: pore_flex_schedule failed. rc = 0x%08x", l_rc);
+ TRAC_ERR("cent_get_enabled_sensors: gpe_request_schedule failed. rc = 0x%08x", l_rc);
break;
}
@@ -980,6 +931,7 @@ int cent_get_enabled_sensors()
{
G_dimm_enabled_sensors.bytes[l_cent] = ((uint8_t*)(&G_cent_scom_data[l_cent]))[0];
}
+ G_dimm_present_sensors = G_dimm_enabled_sensors;
TRAC_IMP("bitmap of enabled dimm temperature sensors: 0x%08X %08X",
G_dimm_enabled_sensors.words[0],
@@ -987,7 +939,6 @@ int cent_get_enabled_sensors()
}while(0);
return l_rc;
}
-#endif // #if 0
// Function Specification
//
@@ -998,15 +949,13 @@ int cent_get_enabled_sensors()
// This will also initialize the centaur watchdog.
//
// End Function Specification
-/* TODO: RTC 163359 - Reenable when needed */
-#if 0
void centaur_init( void )
{
errlHndl_t l_err = NULL; // Error handler
int rc = 0; // Return code
int l_jj = 0; // Indexer
static scomList_t L_scomList[2] SECTION_ATTRIBUTE(".noncacheable");
- static GpeScomParms L_centaur_reg_parms SECTION_ATTRIBUTE(".noncacheable");
+ static CentaurScomParms_t L_centaur_reg_parms SECTION_ATTRIBUTE(".noncacheable");
do
{
@@ -1019,11 +968,9 @@ void centaur_init( void )
/// Before anything else, we need to call this procedure to
/// determine which Centaurs are out there, their config info.
/// and Type/EC Level
-
- rc = centaur_configuration_create();
+ rc = centaur_configuration_create(&G_centaurConfiguration);
if( rc )
{
- TRAC_ERR("centaur_init: Centaur Config Create failed with rc=0x%08x ", rc );
break;
}
@@ -1045,7 +992,7 @@ void centaur_init( void )
G_present_centaurs |= (CENTAUR0_PRESENT_MASK >> l_jj);
// Trace out the CFAM Chip ID, which includes Type & EC
- TRAC_INFO("centaur_init: Centaur[%d] Found, Chip Id=0x%08x",l_jj, mb_id(l_jj));
+ TRAC_INFO("centaur_init: Centaur[%d] Found, Chip Id= 0x%08x",l_jj);
}
}
}
@@ -1057,49 +1004,49 @@ void centaur_init( void )
// Set up recovery scom list entries
G_cent_scom_list_entry[L4_LINE_DELETE].scom = MBCCFGQ_REG; //scom address
- G_cent_scom_list_entry[L4_LINE_DELETE].commandType = GPE_SCOM_RMW; //scom operation to perform
+ G_cent_scom_list_entry[L4_LINE_DELETE].commandType = CENTAUR_SCOM_RMW; //scom operation to perform
G_cent_scom_list_entry[L4_LINE_DELETE].mask = LINE_DELETE_ON_NEXT_CE; //mask of bits to change
G_cent_scom_list_entry[L4_LINE_DELETE].data = LINE_DELETE_ON_NEXT_CE; //scom data (always set the bit)
//one time init for reading LFIR6
G_cent_scom_list_entry[READ_NEST_LFIR6].scom = CENT_NEST_LFIR_REG; //scom address
- G_cent_scom_list_entry[READ_NEST_LFIR6].commandType = GPE_SCOM_READ; //scom operation to perform
+ G_cent_scom_list_entry[READ_NEST_LFIR6].commandType = CENTAUR_SCOM_READ; //scom operation to perform
G_cent_scom_list_entry[READ_NEST_LFIR6].mask = 0; //mask (not used for reads)
G_cent_scom_list_entry[READ_NEST_LFIR6].data = 0; //scom data (initialize to 0)
//one time init for reading centaur thermal status register
G_cent_scom_list_entry[READ_THERM_STATUS].scom = CENT_THRM_STATUS_REG; //scom address
- G_cent_scom_list_entry[READ_THERM_STATUS].commandType = GPE_SCOM_READ; //scom operation to perform
+ G_cent_scom_list_entry[READ_THERM_STATUS].commandType = CENTAUR_SCOM_READ; //scom operation to perform
G_cent_scom_list_entry[READ_THERM_STATUS].mask = 0; //mask (not used for reads)
G_cent_scom_list_entry[READ_THERM_STATUS].data = 0; //scom data (initialize to 0)
//one time init to reset the centaur dts FSM
G_cent_scom_list_entry[RESET_DTS_FSM].scom = CENT_THRM_CTRL_REG; //scom address
- G_cent_scom_list_entry[RESET_DTS_FSM].commandType = GPE_SCOM_NOP; //init to no-op (only runs if needed)
+ G_cent_scom_list_entry[RESET_DTS_FSM].commandType = CENTAUR_SCOM_NOP; //init to no-op (only runs if needed)
G_cent_scom_list_entry[RESET_DTS_FSM].mask = 0; //mask (not used for writes)
G_cent_scom_list_entry[RESET_DTS_FSM].data = CENT_THRM_CTRL4; //scom data (sets bit4)
//one time init to clear centaur NEST LFIR 6
G_cent_scom_list_entry[CLEAR_NEST_LFIR6].scom = CENT_NEST_LFIR_AND_REG; //scom address
- G_cent_scom_list_entry[CLEAR_NEST_LFIR6].commandType = GPE_SCOM_NOP; //init to no-op (only runs if needed)
+ G_cent_scom_list_entry[CLEAR_NEST_LFIR6].commandType = CENTAUR_SCOM_NOP; //init to no-op (only runs if needed)
G_cent_scom_list_entry[CLEAR_NEST_LFIR6].mask = 0; //mask (not used for writes)
G_cent_scom_list_entry[CLEAR_NEST_LFIR6].data = ~CENT_NEST_LFIR6; //scom data
//one time init to disable centaur sensor cache
G_cent_scom_list_entry[DISABLE_SC].scom = SCAC_CONFIG_REG; //scom address
- G_cent_scom_list_entry[DISABLE_SC].commandType = GPE_SCOM_NOP; //init to no-op (only runs if needed)
+ G_cent_scom_list_entry[DISABLE_SC].commandType = CENTAUR_SCOM_NOP; //init to no-op (only runs if needed)
G_cent_scom_list_entry[DISABLE_SC].mask = SCAC_MASTER_ENABLE; //mask of bits to change
G_cent_scom_list_entry[DISABLE_SC].data = 0; //scom data (disable sensor cache)
//one time init to enable centaur sensor cache
G_cent_scom_list_entry[ENABLE_SC].scom = SCAC_CONFIG_REG; //scom address
- G_cent_scom_list_entry[ENABLE_SC].commandType = GPE_SCOM_NOP; //init to no-op (only runs if needed)
+ G_cent_scom_list_entry[ENABLE_SC].commandType = CENTAUR_SCOM_NOP; //init to no-op (only runs if needed)
G_cent_scom_list_entry[ENABLE_SC].mask = SCAC_MASTER_ENABLE; //mask of bits to change
G_cent_scom_list_entry[ENABLE_SC].data = SCAC_MASTER_ENABLE; //scom data (enable sensor cache)
//one time init for reading centaur sensor cache lfir
G_cent_scom_list_entry[READ_SCAC_LFIR].scom = SCAC_LFIR_REG; //scom address
- G_cent_scom_list_entry[READ_SCAC_LFIR].commandType = GPE_SCOM_READ; //scom operation to perform
+ G_cent_scom_list_entry[READ_SCAC_LFIR].commandType = CENTAUR_SCOM_READ; //scom operation to perform
G_cent_scom_list_entry[READ_SCAC_LFIR].mask = 0; //mask (not used for reads)
G_cent_scom_list_entry[READ_SCAC_LFIR].data = 0; //scom data (initialize to 0)
@@ -1108,7 +1055,7 @@ void centaur_init( void )
/// NOTE: max timeout is about 2 seconds.
L_scomList[0].scom = CENTAUR_MBSCFGQ;
- L_scomList[0].commandType = GPE_SCOM_RMW_ALL;
+ L_scomList[0].commandType = CENTAUR_SCOM_RMW_ALL;
centaur_mbscfgq_t l_mbscfg;
l_mbscfg.value = 0;
@@ -1125,7 +1072,7 @@ void centaur_init( void )
/// [1]: clear the emergency throttle bit
L_scomList[1].scom = CENTAUR_MBSEMERTHROQ;
- L_scomList[1].commandType = GPE_SCOM_RMW_ALL;
+ L_scomList[1].commandType = CENTAUR_SCOM_RMW_ALL;
centaur_mbsemerthroq_t l_mbs_et;
l_mbs_et.value = 0;
@@ -1137,40 +1084,39 @@ void centaur_init( void )
l_mbs_et.fields.emergency_throttle_ip = 1;
L_scomList[1].mask = l_mbs_et.value;
- L_centaur_reg_parms.scomList = (uint32_t) (&L_scomList[0]);
+ L_centaur_reg_parms.scomList = &L_scomList[0];
L_centaur_reg_parms.entries = 2;
- L_centaur_reg_parms.options = 0;
- L_centaur_reg_parms.rc = 0;
- L_centaur_reg_parms.errorIndex = 0;
-
- //Initialize PoreFlex
- rc = pore_flex_create( &G_centaur_reg_pore_req, //gpe_req for the task
- &G_pore_gpe1_queue, //queue
- gpe_scom_centaur, //entry point
- (uint32_t) &L_centaur_reg_parms, //parm for the task
- SSX_SECONDS(5), //no timeout
+ L_centaur_reg_parms.error.ffdc = 0;
+
+ //Initialize GPE request
+ rc = gpe_request_create(
+ &G_centaur_reg_gpe_req, //gpe_req for the task
+ &G_async_gpe_queue1, //queue
+ IPC_ST_CENTAUR_SCOM_FUNCID, // Function ID
+ &L_centaur_reg_parms, //parm for the task
+ SSX_SECONDS(5), //timeout
NULL, //callback
NULL, //callback argument
ASYNC_REQUEST_BLOCKING ); //options
if(rc)
{
- TRAC_ERR("centaur_init: pore_flex_create failed for G_centaur_reg_pore_req. rc = 0x%08x", rc);
+ TRAC_ERR("centaur_init: gpe_request_create failed for G_centaur_reg_gpe_req. rc = 0x%08x", rc);
break;
}
// Submit Pore GPE and wait for completion
- rc = pore_flex_schedule(&G_centaur_reg_pore_req);
+ rc = gpe_request_schedule(&G_centaur_reg_gpe_req);
// Check for errors on Scom
- if(rc || L_centaur_reg_parms.rc)
+ if(rc || L_centaur_reg_parms.error.rc)
{
- TRAC_ERR("centaur_init: gpe_scom_centaur failure. rc = 0x%08x, gpe_rc = 0x%08x, index = 0x%08x",
+ TRAC_ERR("centaur_init: IPC_ST_CENTAUR_SCOM failure. rc = 0x%08x, gpe_rc = 0x%08x, address = 0x%08x",
rc,
- L_centaur_reg_parms.rc,
- L_centaur_reg_parms.errorIndex);
+ L_centaur_reg_parms.error.rc,
+ L_centaur_reg_parms.error.addr);
if(!rc)
{
- rc = L_centaur_reg_parms.rc;
+ rc = L_centaur_reg_parms.error.rc;
}
break;
}
@@ -1180,16 +1126,17 @@ void centaur_init( void )
/// to gather the 'centaur' data, but we will set them to
/// invalid (-1) until the task sets them up
- G_centaur_data_parms.rc = 0;
+ G_centaur_data_parms.error.ffdc = 0;
G_centaur_data_parms.collect = -1;
G_centaur_data_parms.update = -1;
G_centaur_data_parms.data = 0;
//Initializes existing PoreFlex object for centaur data
- rc = pore_flex_create( &G_centaur_data_task.gpe_req, //gpe_req for the task
- &G_pore_gpe1_queue, //queue
- gpe_get_mem_data, //entry point
- (uint32_t) &G_centaur_data_parms, //parm for the task
+ rc = gpe_request_create(
+ &G_centaur_data_task.gpe_req, //gpe_req for the task
+ &G_async_gpe_queue1, //queue
+ IPC_ST_CENTAUR_DATA_FUNCID, //Function ID
+ &G_centaur_data_parms, //parm for the task
SSX_WAIT_FOREVER, //
NULL, //callback
NULL, //callback argument
@@ -1197,22 +1144,23 @@ void centaur_init( void )
if(rc)
{
- TRAC_ERR("centaur_init: pore_flex_create failed for G_centaur_data_task.gpe_req. rc = 0x%08x", rc);
+ TRAC_ERR("centaur_init: gpe_request_create failed for G_centaur_data_task.gpe_req. rc = 0x%08x", rc);
break;
}
- //Initialize existing PoreFlex object for centaur recovery
- rc = pore_flex_create( &G_cent_scom_req, // gpe_req for the task
- &G_pore_gpe1_queue, // queue
- gpe_scom_centaur, // entry point
- (uint32_t) &G_cent_scom_gpe_parms, // parm for the task
- SSX_WAIT_FOREVER, //
- NULL, // callback
- NULL, // callback argument
- 0); // options
+ //Initialize existing GpeRequest object for centaur recovery
+ rc = gpe_request_create(
+ &G_cent_scom_req, // gpe_req for the task
+ &G_async_gpe_queue1, // queue
+ IPC_ST_CENTAUR_SCOM_FUNCID, // entry point
+ &G_cent_scom_gpe_parms, // parm for the task
+ SSX_WAIT_FOREVER, //
+ NULL, // callback
+ NULL, // callback argument
+ 0); // options
if(rc)
{
- TRAC_ERR("centaur_init: pore_flex_create failed for G_cent_scom_req. rc = 0x%08x", rc);
+ TRAC_ERR("centaur_init: gpe_request_create failed for G_cent_scom_req. rc = 0x%08x", rc);
break;
}
@@ -1241,15 +1189,23 @@ void centaur_init( void )
NULL, //Trace Buf
DEFAULT_TRACE_SIZE, //Trace Size
rc, //userdata1
- L_centaur_reg_parms.rc //userdata2
+ L_centaur_reg_parms.error.rc //userdata2
);
addUsrDtlsToErrl(l_err, //io_err
- (uint8_t *) &G_centaur_reg_pore_req.ffdc, //i_dataPtr,
- sizeof(PoreFfdc), //i_size
+ (uint8_t *) &G_centaur_reg_gpe_req.ffdc, //i_dataPtr,
+ sizeof(GpeFfdc), //i_size
ERRL_USR_DTL_STRUCT_VERSION_1, //version
ERRL_USR_DTL_BINARY_DATA); //type
+ // Capture the GPE1 trace buffer
+ addUsrDtlsToErrl(l_err,
+ (uint8_t *) G_shared_gpe_data.gpe1_tb_ptr,
+ G_shared_gpe_data.gpe1_tb_sz,
+ ERRL_USR_DTL_STRUCT_VERSION_1,
+ ERRL_USR_DTL_TRACE_DATA);
+
+
REQUEST_RESET(l_err);
}
else
@@ -1261,7 +1217,6 @@ void centaur_init( void )
return;
}
-#endif // #if 0
// Function Specification
//
@@ -1272,9 +1227,7 @@ void centaur_init( void )
// Returns NULL for centaur ID outside the range of 0 to 7.
//
// End Function Specification
-/* TODO: RTC 163359 - Reenable when needed */
-#if 0
-MemData * cent_get_centaur_data_ptr( const uint8_t i_occ_centaur_id )
+CentaurMemData * cent_get_centaur_data_ptr( const uint8_t i_occ_centaur_id )
{
//The caller needs to send in a valid OCC centaur id. Since type is uchar
//so there is no need to check for case less than 0.
@@ -1291,4 +1244,57 @@ MemData * cent_get_centaur_data_ptr( const uint8_t i_occ_centaur_id )
return( NULL );
}
}
-#endif
+
+uint32_t centaur_configuration_create( CentaurConfiguration_t * i_centaurConfiguration )
+{
+ bool rc = 0;
+ GpeRequest l_request;
+
+ do
+ {
+ G_gpe_centaur_config_args.centaurConfiguration = i_centaurConfiguration;
+
+ rc = gpe_request_create(
+ &l_request, // request
+ &G_async_gpe_queue1, // gpe queue
+ IPC_ST_CENTAUR_INIT_FUNCID, // Function Id
+ &G_gpe_centaur_config_args, // GPE arg_ptr
+ SSX_SECONDS(5), // timeout
+ NULL, // callback
+ NULL, // callback arg
+ ASYNC_REQUEST_BLOCKING);
+ if( rc )
+ {
+ TRAC_ERR("centaur_configuration_create: gpe_request_create failed for"
+ " IPC_ST_CENTAUR_INIT_FUNCID. rc = 0x%08x",rc);
+ break;
+ }
+
+ TRAC_INFO("centaur_configuration_create: Scheduling request for IPC_ST_CENTAUR_INIT_FUNCID");
+ gpe_request_schedule(&l_request);
+
+ TRAC_INFO("centaur_configuration_create: GPE_centaur_configuration_create w/rc=0x%08x",
+ l_request.request.completion_state);
+
+ if(ASYNC_REQUEST_STATE_COMPLETE != l_request.request.completion_state)
+ {
+ rc = l_request.request.completion_state;
+
+ TRAC_ERR("centaur_configuration_create: IPC_ST_CENTAUR_INIT_FUNCID"
+ " request did not complete.");
+ break;
+ }
+
+ if (G_gpe_centaur_config_args.error.rc != GPE_RC_SUCCESS)
+ {
+ rc = G_gpe_centaur_config_args.error.rc;
+ TRAC_ERR("centaur_configuration_create: IPC_ST_CENTAUR_INIT_FUNCID"
+ " failed with rc=0x%08x.",
+ rc);
+ break;
+ }
+
+ } while (0);
+
+ return rc;
+}
diff --git a/src/occ_405/cent/centaur_data.h b/src/occ_405/cent/centaur_data.h
index 17831e4..0208265 100755
--- a/src/occ_405/cent/centaur_data.h
+++ b/src/occ_405/cent/centaur_data.h
@@ -32,7 +32,8 @@
#include <occ_common.h>
#include <ssx.h>
#include "rtls.h"
-//#include "gpe_data.h"
+#include "centaur_mem_data.h"
+#include "centaur_structs.h"
#include "occ_sys_config.h"
#include "memory.h"
@@ -107,26 +108,24 @@ enum eOccCentaurs
//*************************************************************************
//Centaur data collect structures used for task data pointers
-// TEMP -- PORE ISSUES
-/*
+
struct centaur_data_task {
uint8_t start_centaur;
uint8_t current_centaur;
uint8_t end_centaur;
uint8_t prev_centaur;
- MemData * centaur_data_ptr;
- PoreFlex gpe_req;
+ CentaurMemData * centaur_data_ptr;
+ GpeRequest gpe_req;
} __attribute__ ((__packed__));
typedef struct centaur_data_task centaur_data_task_t;
-*/
+
//*************************************************************************
// Globals
//*************************************************************************
//Global centaur structures used for task data pointers
-// TEMP -- COMMENTED OUT DUE TO PORE ISSUES
-//extern centaur_data_task_t G_centaur_data_task;
+extern centaur_data_task_t G_centaur_data_task;
//Global is bitmask of centaurs
extern uint32_t G_present_centaurs;
@@ -164,7 +163,7 @@ extern uint16_t G_configured_mbas;
//*************************************************************************
//Collect centaur data for all centaur in specified range
-void task_centaur_data( task_t * i_task );
+void centaur_data( void );
//Initialize structures for collecting centaur data.
//void centaur_init( void ) INIT_SECTION;
@@ -173,14 +172,11 @@ void centaur_init( void );
//handles centaur i2c recovery and other workarounds
void cent_recovery(uint32_t i_cent);
-//Determines if a centaur has a channel checkstop (returns TRUE is it has a
-//channel checkstop, FALSE otherwise)
-bool cent_chan_checkstop(const uint8_t i_cent);
-
//Returns a pointer to the most up-to-date centaur data for the centaur
//associated with the specified OCC centaur id.
-// TEMP -- WHERE IS MemData ??
-//MemData * cent_get_centaur_data_ptr( const uint8_t i_centaur_id );
+CentaurMemData * cent_get_centaur_data_ptr( const uint8_t i_centaur_id );
+
+uint32_t centaur_configuration_create( CentaurConfiguration_t * i_centaurConfiguration );
#endif //_CENTAUR_DATA_H
diff --git a/src/occ_405/cmdh/cmdh_dbug_cmd.c b/src/occ_405/cmdh/cmdh_dbug_cmd.c
index 2015ac8..ac030ae 100755
--- a/src/occ_405/cmdh/cmdh_dbug_cmd.c
+++ b/src/occ_405/cmdh/cmdh_dbug_cmd.c
@@ -35,9 +35,10 @@
#include <cmdh_fsp.h>
#include <cmdh_fsp_cmds.h>
#include <memory.h>
-//#include <gpe_data.h>
+#include <centaur_data.h>
#include <proc_data.h>
#include <apss.h>
+#include "centaur_mem_data.h"
//*************************************************************************/
// Externs
@@ -149,30 +150,27 @@ void dbug_err_inject(const cmdh_fsp_cmd_t * i_cmd_ptr,
void dbug_centaur_dump(const cmdh_fsp_cmd_t * i_cmd_ptr,
cmdh_fsp_rsp_t * i_rsp_ptr)
{
-/* TODO - RTC 163359 Centaur support */
-#if 0
uint16_t l_datalen = 0;
uint8_t l_jj=0;
// Determine the size of the data we are returning
- l_datalen = (sizeof(MemData) * MAX_NUM_CENTAURS);
+ l_datalen = (sizeof(CentaurMemData) * MAX_NUM_CENTAURS);
// Fill out the response with the data we are returning
for(l_jj=0; l_jj < MAX_NUM_CENTAURS; l_jj++)
{
- MemData * l_sensor_cache_ptr =
+ CentaurMemData * l_sensor_cache_ptr =
cent_get_centaur_data_ptr(l_jj);
- memcpy((void *)&(i_rsp_ptr->data[l_jj*sizeof(MemData)]),
+ memcpy((void *)&(i_rsp_ptr->data[l_jj*sizeof(CentaurMemData)]),
(void *)l_sensor_cache_ptr,
- sizeof(MemData));
+ sizeof(CentaurMemData));
}
// Fill out the rest of the response data
i_rsp_ptr->data_length[0] = CONVERT_UINT16_UINT8_HIGH(l_datalen);
i_rsp_ptr->data_length[1] = CONVERT_UINT16_UINT8_LOW(l_datalen);
G_rsp_status = ERRL_RC_SUCCESS;
-#endif
return;
}
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds.c b/src/occ_405/cmdh/cmdh_fsp_cmds.c
index 6253652..c1cfd8e 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds.c
@@ -58,6 +58,7 @@ extern uint32_t G_first_proc_gpu_config;
extern bool G_vrm_vdd_temp_expired;
extern bool G_reset_prep;
extern uint16_t G_amester_max_data_length;
+extern uint8_t G_occ_interrupt_type;
#include <gpe_export.h>
extern gpe_shared_data_t G_shared_gpe_data;
@@ -156,8 +157,8 @@ errlHndl_t cmdh_tmgt_poll (const cmdh_fsp_cmd_t * i_cmd_ptr,
ERRL_RC cmdh_poll_v20(cmdh_fsp_rsp_t * o_rsp_ptr)
{
ERRL_RC l_rc = ERRL_RC_INTERNAL_FAIL;
- uint8_t k = 0, l_max_sensors = 0;
- uint8_t l_err_hist_idx = 0, l_sens_list_idx = 0;
+ int k = 0, l_max_sensors = 0;
+ int l_err_hist_idx = 0, l_sens_list_idx = 0;
cmdh_poll_sensor_db_t l_sensorHeader;
// Set pointer to start of o_rsp_ptr
@@ -330,7 +331,8 @@ ERRL_RC cmdh_poll_v20(cmdh_fsp_rsp_t * o_rsp_ptr)
if (CENTAUR_PRESENT(l_cent))
{
//Add entry for centaurs.
- l_tempSensorList[l_sensorHeader.count].id = g_amec->proc[0].memctl[l_cent].centaur.temp_sid;
+ uint32_t l_temp_sid = g_amec->proc[0].memctl[l_cent].centaur.temp_sid;
+ l_tempSensorList[l_sensorHeader.count].id = l_temp_sid;
l_tempSensorList[l_sensorHeader.count].fru_type = DATA_FRU_CENTAUR;
if (G_cent_timeout_logged_bitmap & (CENTAUR0_PRESENT_MASK >> l_cent))
{
@@ -340,14 +342,23 @@ ERRL_RC cmdh_poll_v20(cmdh_fsp_rsp_t * o_rsp_ptr)
{
l_tempSensorList[l_sensorHeader.count].value = (g_amec->proc[0].memctl[l_cent].centaur.centaur_hottest.cur_temp) & 0xFF;
}
+
l_sensorHeader.count++;
//Add entries for present dimms associated with current centaur l_cent.
for(l_dimm=0; l_dimm < NUM_DIMMS_PER_CENTAUR; l_dimm++)
{
- if (g_amec->proc[0].memctl[l_cent].centaur.dimm_temps[l_dimm].temp_sid != 0)
+ l_temp_sid = g_amec->proc[0].memctl[l_cent].centaur.dimm_temps[l_dimm].temp_sid;
+
+ // TODO temp fix until the dimm numbering gets sorted out
+ if(FSP_SUPPORTED_OCC == G_occ_interrupt_type && l_temp_sid == 0)
+ {
+ l_temp_sid = 1 + l_dimm; // If sid is zero them make up a sid for FSP
+ }
+
+ if (l_temp_sid != 0)
{
- l_tempSensorList[l_sensorHeader.count].id = g_amec->proc[0].memctl[l_cent].centaur.dimm_temps[l_dimm].temp_sid;
+ l_tempSensorList[l_sensorHeader.count].id = l_temp_sid;
l_tempSensorList[l_sensorHeader.count].fru_type = DATA_FRU_DIMM;
//If a dimm timed out long enough, we should return 0xFFFF for that sensor.
if (G_dimm_temp_expired_bitmap.bytes[l_cent] & (DIMM_SENSOR0 >> l_dimm))
@@ -454,7 +465,7 @@ ERRL_RC cmdh_poll_v20(cmdh_fsp_rsp_t * o_rsp_ptr)
// Write data to resp buffer if any.
if (l_sensorHeader.count)
{
- uint8_t l_sensordataSz = l_sensorHeader.count * l_sensorHeader.length;
+ int l_sensordataSz = l_sensorHeader.count * l_sensorHeader.length;
// Copy sensor data into response buffer.
memcpy ((void *) &(o_rsp_ptr->data[l_rsp_index]), (void *)l_tempSensorList, l_sensordataSz);
// Increment index into response buffer.
@@ -490,7 +501,7 @@ ERRL_RC cmdh_poll_v20(cmdh_fsp_rsp_t * o_rsp_ptr)
// Write data to outbuffer if any.
if (l_sensorHeader.count)
{
- uint8_t l_sensordataSz = l_sensorHeader.count * l_sensorHeader.length;
+ int l_sensordataSz = l_sensorHeader.count * l_sensorHeader.length;
// Copy sensor data into response buffer.
memcpy ((void *) &(o_rsp_ptr->data[l_rsp_index]), (void *)l_freqSensorList, l_sensordataSz);
// Increment index into response buffer.
@@ -779,7 +790,7 @@ ERRL_RC cmdh_poll_v20(cmdh_fsp_rsp_t * o_rsp_ptr)
// Write data to outbuffer if any.
if (l_sensorHeader.count)
{
- uint8_t l_sensordataSz = l_sensorHeader.count * l_sensorHeader.length;
+ int l_sensordataSz = l_sensorHeader.count * l_sensorHeader.length;
// Copy sensor data into response buffer.
memcpy ((void *) &(o_rsp_ptr->data[l_rsp_index]), (void *)l_extnSensorList, l_sensordataSz);
// Increment index into response buffer.
@@ -966,7 +977,7 @@ errlHndl_t cmdh_clear_elog (const cmdh_fsp_cmd_t * i_cmd_ptr,
cmdh_fsp_rsp_t * o_rsp_ptr)
{
cmdh_clear_elog_query_t *l_cmd_ptr = (cmdh_clear_elog_query_t *) i_cmd_ptr;
- uint8_t l_SlotNum = ERRL_INVALID_SLOT;
+ int l_SlotNum = ERRL_INVALID_SLOT;
errlHndl_t l_err = INVALID_ERR_HNDL;
errlHndl_t l_oci_address = INVALID_ERR_HNDL;
@@ -1067,7 +1078,7 @@ void cmdh_dbug_get_trace (const cmdh_fsp_cmd_t * i_cmd_ptr,
void cmdh_dbug_get_ame_sensor (const cmdh_fsp_cmd_t * i_cmd_ptr,
cmdh_fsp_rsp_t * o_rsp_ptr)
{
- uint8_t l_rc = ERRL_RC_SUCCESS;
+ int l_rc = ERRL_RC_SUCCESS;
uint16_t l_type = 0;
uint16_t l_location = 0;
uint16_t i = 0;
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
index 0a54511..542b5bc 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
@@ -2052,16 +2052,7 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
}
else
{
- // TODO: RTC 163359 - OCC Centaur Support
- //G_sysConfigData.mem_type = MEM_TYPE_CUMULUS;
-
- CMDH_TRAC_ERR("data_store_mem_cfg: Invalid mem type 0x%02X in config data packet version[0x%02X] num_data_sets[%u]",
- data_sets_ptr[0].memory_type,
- l_cmd_ptr->header.version,
- num_data_sets);
-
- cmdh_build_errl_rsp(i_cmd_ptr, o_rsp_ptr, ERRL_RC_INVALID_DATA, &l_err);
- break;
+ G_sysConfigData.mem_type = MEM_TYPE_CUMULUS;
}
// Store the hardware sensor ID and the temperature sensor ID
@@ -2156,16 +2147,8 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
}
else // must be cumulus and the "memory type" byte is the centaur#
{
- CMDH_TRAC_ERR("data_store_mem_cfg: Invalid mem type 0x%02X in config data packet entry %d (entry 0 type: 0x%02X)",
- l_data_set->memory_type, i, G_sysConfigData.mem_type);
-
- cmdh_build_errl_rsp(i_cmd_ptr, o_rsp_ptr, ERRL_RC_INVALID_DATA, &l_err);
- break;
-
-#if 0
- // TODO: RTC 163359 - OCC Centaur Support
// per spec for cumulus memory type is the centaur# and dimm info1 is DIMM#
- uint8_t l_centaur_num = l_data_set->memory_type;
+ int l_centaur_num = l_data_set->memory_type;
l_dimm_num = l_data_set->dimm_info1;
// Validate the centaur and dimm #'s for this data set
@@ -2202,7 +2185,7 @@ errlHndl_t data_store_mem_cfg(const cmdh_fsp_cmd_t * i_cmd_ptr,
l_num_dimms++;
}
-#endif
+
} // Cumulus
} // for each data set
} // else no data sets given
diff --git a/src/occ_405/dimm/dimm.c b/src/occ_405/dimm/dimm.c
index 40af9de..2e1158d 100755
--- a/src/occ_405/dimm/dimm.c
+++ b/src/occ_405/dimm/dimm.c
@@ -746,265 +746,272 @@ void task_dimm_sm(struct task *i_self)
#ifdef DEBUG_LOCK_TESTING
SIMULATE_HOST();
#endif
-
- // First handle any outstanding I2C reset
- if (G_dimm_i2c_reset_required)
+ if (MEM_TYPE_NIMBUS == G_sysConfigData.mem_type)
{
- if ((G_dimm_state != DIMM_STATE_RESET_MASTER) && (check_for_i2c_failure()))
- {
- // I2C failure occurred during a reset...
- INTR_TRAC_ERR("task_dimm_sm: Failure during I2C reset - memory monitoring disabled");
- // release I2C lock to the host for this engine and stop monitoring
- L_occ_owns_lock = false;
- disable_all_dimms();
- }
- else
+
+ // First handle any outstanding I2C reset
+ if (G_dimm_i2c_reset_required)
{
- if (G_dimm_state == DIMM_STATE_INIT)
+ if ((G_dimm_state != DIMM_STATE_RESET_MASTER) && (check_for_i2c_failure()))
{
- // Reset has completed successfully
- TRAC_INFO("task_dimm_sm: I2C reset completed");
- G_dimm_i2c_reset_required = false;
- // Check if host needs I2C lock
- L_occ_owns_lock = check_and_update_i2c_lock(engine);
+ // I2C failure occurred during a reset...
+ INTR_TRAC_ERR("task_dimm_sm: Failure during I2C reset - memory monitoring disabled");
+ // release I2C lock to the host for this engine and stop monitoring
+ L_occ_owns_lock = false;
+ disable_all_dimms();
}
else
{
- // Reset still in progress
- G_dimm_state = dimm_reset_sm();
+ if (G_dimm_state == DIMM_STATE_INIT)
+ {
+ // Reset has completed successfully
+ TRAC_INFO("task_dimm_sm: I2C reset completed");
+ G_dimm_i2c_reset_required = false;
+ // Check if host needs I2C lock
+ L_occ_owns_lock = check_and_update_i2c_lock(engine);
+ }
+ else
+ {
+ // Reset still in progress
+ G_dimm_state = dimm_reset_sm();
+ }
}
}
- }
- if (G_dimm_i2c_reset_required == false)
- {
- if ((L_occ_owns_lock == false) && ((DIMM_TICK == 0) || (DIMM_TICK == 8)))
+ if (G_dimm_i2c_reset_required == false)
{
- // Check if host gave up the I2C lock
- L_occ_owns_lock = check_and_update_i2c_lock(engine);
- if (L_occ_owns_lock)
+ if ((L_occ_owns_lock == false) && ((DIMM_TICK == 0) || (DIMM_TICK == 8)))
{
- // Start over at the INIT state after receiving the lock
- G_dimm_state = DIMM_STATE_INIT;
+ // Check if host gave up the I2C lock
+ L_occ_owns_lock = check_and_update_i2c_lock(engine);
+ if (L_occ_owns_lock)
+ {
+ // Start over at the INIT state after receiving the lock
+ G_dimm_state = DIMM_STATE_INIT;
+ }
}
- }
- if (L_occ_owns_lock)
- {
- // Check for failure on prior operation
- if (check_for_i2c_failure())
+ if (L_occ_owns_lock)
{
- // If there was a failure, continue to the next DIMM (after I2c reset)
- use_next_dimm(&L_dimmPort, &L_dimmIndex);
- }
+ // Check for failure on prior operation
+ if (check_for_i2c_failure())
+ {
+ // If there was a failure, continue to the next DIMM (after I2c reset)
+ use_next_dimm(&L_dimmPort, &L_dimmIndex);
+ }
- uint8_t nextState = G_dimm_state;
- static dimm_sm_args_t L_new_dimm_args = {{{{0}}}};
+ uint8_t nextState = G_dimm_state;
+ static dimm_sm_args_t L_new_dimm_args = {{{{0}}}};
- if (G_dimm_state == DIMM_STATE_INIT)
- {
- // Setup I2C Interrupt Mask Register
- DIMM_DBG("DIMM_STATE_INIT: (I2C Engine 0x%02X, Memory Type 0x%02X)",
- engine, G_sysConfigData.mem_type);
- L_new_dimm_args.i2cEngine = engine;
- if (schedule_dimm_req(DIMM_STATE_INIT, L_new_dimm_args))
+ if (G_dimm_state == DIMM_STATE_INIT)
{
- nextState = DIMM_STATE_WRITE_MODE;
+ // Setup I2C Interrupt Mask Register
+ DIMM_DBG("DIMM_STATE_INIT: (I2C Engine 0x%02X, Memory Type 0x%02X)",
+ engine, G_sysConfigData.mem_type);
+ L_new_dimm_args.i2cEngine = engine;
+ if (schedule_dimm_req(DIMM_STATE_INIT, L_new_dimm_args))
+ {
+ nextState = DIMM_STATE_WRITE_MODE;
+ }
}
- }
- else
- {
- bool intTriggered = check_for_i2c_interrupt(engine);
- if (intTriggered == false)
+ else
{
- // Interrupt not generated, I2C operation may not have completed.
- // After MAX_TICK_COUNT_WAIT, attempt operation anyway.
- ++L_notReadyCount;
- }
+ bool intTriggered = check_for_i2c_interrupt(engine);
+ if (intTriggered == false)
+ {
+ // Interrupt not generated, I2C operation may not have completed.
+ // After MAX_TICK_COUNT_WAIT, attempt operation anyway.
+ ++L_notReadyCount;
+ }
- // Check if prior command completed (or timed out waiting for it)
- if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
- {
- if (ASYNC_REQUEST_STATE_COMPLETE == G_dimm_sm_request.request.completion_state)
+ // Check if prior command completed (or timed out waiting for it)
+ if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
{
- // IPC request completed, now check return code
- if (GPE_RC_SUCCESS == G_dimm_sm_args.error.rc)
+ if (ASYNC_REQUEST_STATE_COMPLETE == G_dimm_sm_request.request.completion_state)
{
- // last request completed without error
- switch (G_dimm_sm_args.state)
+ // IPC request completed, now check return code
+ if (GPE_RC_SUCCESS == G_dimm_sm_args.error.rc)
{
- case DIMM_STATE_INIT:
- // Save max I2C ports
- if (G_maxDimmPort != G_dimm_sm_args.maxPorts)
- {
- G_maxDimmPort = G_dimm_sm_args.maxPorts;
- DIMM_DBG("task_dimm_sm: updating DIMM Max I2C Port to %d", G_maxDimmPort);
- }
- break;
+ // last request completed without error
+ switch (G_dimm_sm_args.state)
+ {
+ case DIMM_STATE_INIT:
+ // Save max I2C ports
+ if (G_maxDimmPort != G_dimm_sm_args.maxPorts)
+ {
+ G_maxDimmPort = G_dimm_sm_args.maxPorts;
+ DIMM_DBG("task_dimm_sm: updating DIMM Max I2C Port to %d", G_maxDimmPort);
+ }
+ break;
- case DIMM_STATE_READ_TEMP:
- if (L_readIssued)
- {
- // Validate and store temperature
- process_dimm_temp();
+ case DIMM_STATE_READ_TEMP:
+ if (L_readIssued)
+ {
+ // Validate and store temperature
+ process_dimm_temp();
- // Move on to next DIMM
- use_next_dimm(&L_dimmPort, &L_dimmIndex);
- L_readIssued = false;
+ // Move on to next DIMM
+ use_next_dimm(&L_dimmPort, &L_dimmIndex);
+ L_readIssued = false;
- // Check if host needs the I2C lock
- L_occ_owns_lock = check_and_update_i2c_lock(engine);
- }
- break;
+ // Check if host needs the I2C lock
+ L_occ_owns_lock = check_and_update_i2c_lock(engine);
+ }
+ break;
- default:
- // Nothing to do
- break;
+ default:
+ // Nothing to do
+ break;
+ }
}
- }
- else
- {
- // last request did not return success
- switch (G_dimm_sm_args.state)
+ else
{
- case DIMM_STATE_INITIATE_READ:
- if (++L_readAttempt < MAX_READ_ATTEMPT)
- {
- // The initiate_read didnt complete, retry
- DIMM_DBG("task_dimm_sm: initiate read didn't start (%d attempts)", L_readAttempt);
- // Force the read again
- G_dimm_state = DIMM_STATE_INITIATE_READ;
- nextState = G_dimm_state;
- }
- else
- {
- INTR_TRAC_ERR("task_dimm_sm: initiate read didn't start after %d attempts... forcing reset", L_readAttempt);
- mark_dimm_failed();
- }
- break;
-
- case DIMM_STATE_READ_TEMP:
- if (L_readIssued)
- {
+ // last request did not return success
+ switch (G_dimm_sm_args.state)
+ {
+ case DIMM_STATE_INITIATE_READ:
if (++L_readAttempt < MAX_READ_ATTEMPT)
{
- DIMM_DBG("task_dimm_sm: read didn't complete (%d attempts)", L_readAttempt);
+ // The initiate_read didnt complete, retry
+ DIMM_DBG("task_dimm_sm: initiate read didn't start (%d attempts)", L_readAttempt);
// Force the read again
- G_dimm_state = DIMM_STATE_READ_TEMP;
+ G_dimm_state = DIMM_STATE_INITIATE_READ;
nextState = G_dimm_state;
}
else
{
- INTR_TRAC_ERR("task_dimm_sm: read did not complete after %d attempts... forcing reset", L_readAttempt);
+ INTR_TRAC_ERR("task_dimm_sm: initiate read didn't start after %d attempts... forcing reset", L_readAttempt);
mark_dimm_failed();
}
- }
- break;
+ break;
- default:
- // Nothing to do
- break;
+ case DIMM_STATE_READ_TEMP:
+ if (L_readIssued)
+ {
+ if (++L_readAttempt < MAX_READ_ATTEMPT)
+ {
+ DIMM_DBG("task_dimm_sm: read didn't complete (%d attempts)", L_readAttempt);
+ // Force the read again
+ G_dimm_state = DIMM_STATE_READ_TEMP;
+ nextState = G_dimm_state;
+ }
+ else
+ {
+ INTR_TRAC_ERR("task_dimm_sm: read did not complete after %d attempts... forcing reset", L_readAttempt);
+ mark_dimm_failed();
+ }
+ }
+ break;
+
+ default:
+ // Nothing to do
+ break;
+ }
}
}
}
- }
- if (L_occ_owns_lock)
- {
- if (false == G_dimm_i2c_reset_required)
+ if (L_occ_owns_lock)
{
- // Handle new DIMM state
- switch (G_dimm_state)
+ if (false == G_dimm_i2c_reset_required)
{
- case DIMM_STATE_WRITE_MODE:
- // Only start a DIMM read on tick 0 or 8
- if ((DIMM_TICK == 0) || (DIMM_TICK == 8))
- {
- // If DIMM has huid/sensor then it should be present
- // and if not disabled yet, start temp collection
- if (NIMBUS_DIMM_PRESENT(L_dimmPort,L_dimmIndex) &&
- (G_dimm[L_dimmPort][L_dimmIndex].disabled == false))
+ // Handle new DIMM state
+ switch (G_dimm_state)
+ {
+ case DIMM_STATE_WRITE_MODE:
+ // Only start a DIMM read on tick 0 or 8
+ if ((DIMM_TICK == 0) || (DIMM_TICK == 8))
{
- L_new_dimm_args.i2cPort = L_dimmPort;
- L_new_dimm_args.dimm = L_dimmIndex;
- if (schedule_dimm_req(DIMM_STATE_WRITE_MODE, L_new_dimm_args))
+ // If DIMM has huid/sensor then it should be present
+ // and if not disabled yet, start temp collection
+ if (NIMBUS_DIMM_PRESENT(L_dimmPort,L_dimmIndex) &&
+ (G_dimm[L_dimmPort][L_dimmIndex].disabled == false))
{
- DIMM_DBG("task_dimm_sm: Collection started for DIMM%04X at tick %d",
- DIMM_AND_PORT, DIMM_TICK);
- nextState = DIMM_STATE_WRITE_ADDR;
+ L_new_dimm_args.i2cPort = L_dimmPort;
+ L_new_dimm_args.dimm = L_dimmIndex;
+ if (schedule_dimm_req(DIMM_STATE_WRITE_MODE, L_new_dimm_args))
+ {
+ DIMM_DBG("task_dimm_sm: Collection started for DIMM%04X at tick %d",
+ DIMM_AND_PORT, DIMM_TICK);
+ nextState = DIMM_STATE_WRITE_ADDR;
+ }
+ }
+ else
+ {
+ // Skip current DIMM and move on to next one
+ use_next_dimm(&L_dimmPort, &L_dimmIndex);
}
}
- else
- {
- // Skip current DIMM and move on to next one
- use_next_dimm(&L_dimmPort, &L_dimmIndex);
- }
- }
- break;
+ break;
- case DIMM_STATE_WRITE_ADDR:
- if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
- {
- L_new_dimm_args.dimm = L_dimmIndex;
- L_new_dimm_args.i2cAddr = get_dimm_addr(L_dimmIndex);
- if (schedule_dimm_req(DIMM_STATE_WRITE_ADDR, L_new_dimm_args))
+ case DIMM_STATE_WRITE_ADDR:
+ if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
{
- nextState = DIMM_STATE_INITIATE_READ;
- L_readAttempt = 0;
- L_readIssued = false;
+ L_new_dimm_args.dimm = L_dimmIndex;
+ L_new_dimm_args.i2cAddr = get_dimm_addr(L_dimmIndex);
+ if (schedule_dimm_req(DIMM_STATE_WRITE_ADDR, L_new_dimm_args))
+ {
+ nextState = DIMM_STATE_INITIATE_READ;
+ L_readAttempt = 0;
+ L_readIssued = false;
+ }
}
- }
- break;
+ break;
- case DIMM_STATE_INITIATE_READ:
- if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
- {
- L_new_dimm_args.dimm = L_dimmIndex;
- if (schedule_dimm_req(DIMM_STATE_INITIATE_READ, L_new_dimm_args))
+ case DIMM_STATE_INITIATE_READ:
+ if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
{
- nextState = DIMM_STATE_READ_TEMP;
+ L_new_dimm_args.dimm = L_dimmIndex;
+ if (schedule_dimm_req(DIMM_STATE_INITIATE_READ, L_new_dimm_args))
+ {
+ nextState = DIMM_STATE_READ_TEMP;
+ }
}
- }
- break;
+ break;
- case DIMM_STATE_READ_TEMP:
- if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
- {
- if (schedule_dimm_req(DIMM_STATE_READ_TEMP, L_new_dimm_args))
+ case DIMM_STATE_READ_TEMP:
+ if (intTriggered || (L_notReadyCount > MAX_TICK_COUNT_WAIT))
{
- L_readIssued = true;
- nextState = DIMM_STATE_WRITE_MODE;
+ if (schedule_dimm_req(DIMM_STATE_READ_TEMP, L_new_dimm_args))
+ {
+ L_readIssued = true;
+ nextState = DIMM_STATE_WRITE_MODE;
+ }
}
- }
- break;
+ break;
- default:
- INTR_TRAC_ERR("task_dimm_sm: INVALID STATE: 0x%02X", G_dimm_state);
- break;
+ default:
+ INTR_TRAC_ERR("task_dimm_sm: INVALID STATE: 0x%02X", G_dimm_state);
+ break;
+ }
+ }
+ else
+ {
+ // Previous op triggered reset
+ nextState = dimm_reset_sm();
}
}
else
{
- // Previous op triggered reset
- nextState = dimm_reset_sm();
+ // OCC no longer holds the i2c lock (no DIMM state change required)
+ nextState = G_dimm_state;
}
}
- else
+
+ if (nextState != G_dimm_state)
{
- // OCC no longer holds the i2c lock (no DIMM state change required)
- nextState = G_dimm_state;
+ DIMM_DBG("task_dimm_sm: Updating state to 0x%02X (DIMM%04X) end of tick %d", nextState, (L_dimmPort<<8)|L_dimmIndex, DIMM_TICK);
+ G_dimm_state = nextState;
+ L_notReadyCount = 0;
}
}
-
- if (nextState != G_dimm_state)
- {
- DIMM_DBG("task_dimm_sm: Updating state to 0x%02X (DIMM%04X) end of tick %d", nextState, (L_dimmPort<<8)|L_dimmIndex, DIMM_TICK);
- G_dimm_state = nextState;
- L_notReadyCount = 0;
- }
}
}
+ else // G_sysConfigData.mem_type is Centaur
+ {
+ centaur_data();
+ }
}
} // end task_dimm_sm()
diff --git a/src/occ_405/mem/memory.c b/src/occ_405/mem/memory.c
index 4f0e9c6..d485fc8 100644
--- a/src/occ_405/mem/memory.c
+++ b/src/occ_405/mem/memory.c
@@ -31,6 +31,7 @@
#include "dimm_control.h"
#include "centaur_control.h"
#include "centaur_data.h"
+#include "centaur_structs.h"
#include "memory_service_codes.h"
#include <occ_service_codes.h> // for SSX_GENERIC_FAILURE
#include "amec_sys.h"
@@ -40,8 +41,7 @@ extern dimm_control_args_t G_dimm_control_args;
extern task_t G_task_table[TASK_END];
-// TODO: RTC 163359 - uncomment when Centaur code is enabled
-//extern GpeScomParms G_centaur_control_reg_parms;
+extern CentaurScomParms_t G_centaur_control_reg_parms;
// This array identifies dimm throttle limits for both Centaurs (Cumulus) and
// rdimms (Nimbus) based systems.
@@ -106,8 +106,7 @@ void task_memory_control( task_t * i_task )
}
else if (MEM_TYPE_CUMULUS == G_sysConfigData.mem_type)
{
-// TODO: RTC 163359 - uncomment when Centaur code is enabled
-// gpe_rc = G_centaur_control_reg_parms.rc;
+ gpe_rc = G_centaur_control_reg_parms.error.rc;
}
do
@@ -152,12 +151,10 @@ void task_memory_control( task_t * i_task )
{
if(!(L_gpe_fail_logged & (CENTAUR0_PRESENT_MASK >> memIndex)))
{
-// TODO: RTC 163359 - uncomment when Centaur code is enabled
-/* if (!check_centaur_checkstop(memIndex))
+ if (!check_centaur_checkstop(memControlTask))
{
L_gpe_fail_logged |= CENTAUR0_PRESENT_MASK >> memIndex;
- }
-*/
+ }
}
}
//Request failed. Keep count of failures and request a reset if we reach a
@@ -227,8 +224,7 @@ void task_memory_control( task_t * i_task )
{
break;
}
-// TODO RTC: 163359 - centaur code not ready yet
-// rc = centaur_control(memIndex); // Control one centaur
+ rc = centaur_control(memControlTask); // Control one centaur
}
if(rc)
@@ -243,8 +239,7 @@ void task_memory_control( task_t * i_task )
}
else if (MEM_TYPE_CUMULUS == G_sysConfigData.mem_type)
{
-// TODO RTC: 163359 - uncomment when Centaur code is enabled
-// gpe_rc = G_centaur_control_reg_parms.rc;
+ gpe_rc = G_centaur_control_reg_parms.error.rc;
}
//Error in schedule gpe memory (dimm/centaur) control
@@ -370,29 +365,8 @@ void memory_init()
}
else
{
- // TODO RTC: 163359 - CUMULUS NOT SUPPORTED YET IN PHASE1
-#if 0
TRAC_INFO("memory_init: calling centaur_init()");
centaur_init(); //no rc, handles errors internally
-#endif
- TRAC_ERR("memory_init: invalid memory type 0x%02X", G_sysConfigData.mem_type);
- /*
- * @errortype
- * @moduleid MEM_MID_MEMORY_INIT
- * @reasoncode MEMORY_INIT_FAILED
- * @userdata1 memory type
- * @userdata2 0
- * @devdesc Invalid memory type detected
- */
- errlHndl_t err = createErrl(MEM_MID_MEMORY_INIT,
- MEMORY_INIT_FAILED,
- OCC_NO_EXTENDED_RC,
- ERRL_SEV_PREDICTIVE,
- NULL,
- DEFAULT_TRACE_SIZE,
- G_sysConfigData.mem_type,
- 0);
- REQUEST_RESET(err);
}
// check if the init resulted in a reset
diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c
index 499a0c1..8131806 100755
--- a/src/occ_405/occbuildname.c
+++ b/src/occ_405/occbuildname.c
@@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) =
#else
-volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_180301a\0" /*</BuildName>*/ ;
+volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_180328a\0" /*</BuildName>*/ ;
#endif
diff --git a/src/occ_405/sensor/sensor_enum.h b/src/occ_405/sensor/sensor_enum.h
index 51439b1..4cf6a43 100755
--- a/src/occ_405/sensor/sensor_enum.h
+++ b/src/occ_405/sensor/sensor_enum.h
@@ -526,8 +526,6 @@ enum e_gsid
TEMPDIMM14,
TEMPDIMM15,
- // TODO: RTC 163359 - Determine if we want to store individual DIMM temps for CENTAUR
- // or continue to use max DIMM temp/location under each CENTAUR.
TEMPDIMMAXM0,
TEMPDIMMAXM1,
TEMPDIMMAXM2,
diff --git a/src/occ_gpe1/gpe1_main.c b/src/occ_gpe1/gpe1_main.c
index 6272621..326ae42 100644
--- a/src/occ_gpe1/gpe1_main.c
+++ b/src/occ_gpe1/gpe1_main.c
@@ -33,10 +33,11 @@
#include "pk_trace.h"
#include "ipc_api.h"
#include "gpe_export.h"
+#include "gpe_centaur.h"
#define KERNEL_STACK_SIZE 512
-uint8_t G_kernel_stack[KERNEL_STACK_SIZE];
+uint64_t G_kernel_stack[KERNEL_STACK_SIZE/8];
//Point to the GPE shared structure
#define GPE_SHARED_DATA_ADDR 0xFFFB3C00
diff --git a/src/occ_gpe1/gpe_centaur.c b/src/occ_gpe1/gpe_centaur.c
new file mode 100644
index 0000000..671b30d
--- /dev/null
+++ b/src/occ_gpe1/gpe_centaur.c
@@ -0,0 +1,89 @@
+#include "gpe_centaur.h"
+#include "ipc_async_cmd.h"
+#include "gpe_util.h"
+
+CentaurConfiguration_t * G_centaur_config = NULL;
+
+void gpe_centaur_init(ipc_msg_t* i_cmd, void* i_arg)
+{
+ int rc;
+ ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)i_cmd;
+ CentaurConfigParms_t* payload = (CentaurConfigParms_t*)async_cmd->cmd_data;
+
+ CentaurConfiguration_t * config = payload->centaurConfiguration;
+ G_centaur_config = config;
+
+ payload->error.error = 0;
+ payload->error.ffdc = 0;
+
+ if(G_centaur_config == NULL)
+ {
+ PK_TRACE("gpe_centaur_init: centaurConfiguration data ptr is NULL!");
+ rc = GPE_RC_CONFIG_DATA_NULL_PTR;
+ }
+ else
+ {
+ rc = gpe_centaur_configuration_create(G_centaur_config);
+ }
+
+ payload->error.rc = rc;
+
+ // Send response
+ rc = ipc_send_rsp(i_cmd, IPC_RC_SUCCESS);
+ if(rc)
+ {
+ PK_TRACE("gpe_centaur_init: Failed to send response. rc = %x. Halting GPE1.",
+ rc);
+
+ gpe_set_ffdc(&(payload->error), 0x00, GPE_RC_IPC_SEND_FAILED, rc);
+ pk_halt();
+ }
+}
+
+void gpe_centaur_scom(ipc_msg_t* i_cmd, void* i_arg)
+{
+ int rc;
+ ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)i_cmd;
+ CentaurScomParms_t * scomParms = (CentaurScomParms_t*)async_cmd->cmd_data;
+
+ gpe_scom_centaur(G_centaur_config, scomParms);
+
+ // Send response
+ rc = ipc_send_rsp(i_cmd, IPC_RC_SUCCESS);
+ if(rc)
+ {
+ PK_TRACE("gpe_centaur_scom: Failed to send response. rc = %x. Halting GPE1.",
+ rc);
+
+ gpe_set_ffdc(&(scomParms->error), 0x00, GPE_RC_IPC_SEND_FAILED, rc);
+ pk_halt();
+ }
+
+
+}
+
+void gpe_centaur_data(ipc_msg_t* i_cmd, void* i_arg)
+{
+ int rc;
+ ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)i_cmd;
+
+ CentaurGetMemDataParms_t * dataParms =
+ (CentaurGetMemDataParms_t *)async_cmd->cmd_data;
+
+ rc = centaur_get_mem_data(G_centaur_config, dataParms);
+
+ dataParms->error.rc = rc;
+
+ // Send response
+ rc = ipc_send_rsp(i_cmd, IPC_RC_SUCCESS);
+ if(rc)
+ {
+ PK_TRACE("gpe_centaur_init: Failed to send response. rc = %x. Halting GPE1.",
+ rc);
+
+ gpe_set_ffdc(&(dataParms->error), 0x00, GPE_RC_IPC_SEND_FAILED, rc);
+ pk_halt();
+ }
+}
+
+
diff --git a/src/occ_gpe1/gpe_centaur.h b/src/occ_gpe1/gpe_centaur.h
new file mode 100644
index 0000000..ad8e2a7
--- /dev/null
+++ b/src/occ_gpe1/gpe_centaur.h
@@ -0,0 +1,53 @@
+#if !defined(_GPE_CENTAUR_H)
+#define _GPE_CENTAUR_H
+
+#include "ipc_structs.h"
+#include "centaur_structs.h"
+
+// IPC interface
+void gpe_centaur_scom(ipc_msg_t* i_cmd, void* i_arg);
+void gpe_centaur_data(ipc_msg_t* i_cmd, void* i_arg);
+void gpe_centaur_init(ipc_msg_t* i_cmd, void* i_arg);
+
+// HCODE interface
+/**
+ * Populate a CentaurConfiguration object
+ * @param[out] 8 byte aligned pointer to the CentaurConfiguration object.
+ * @return [0 | return code]
+ * @note The CentaurConfiguration object is shared with the 405 so
+ * it needs to be in non-cacheable sram.
+ */
+int gpe_centaur_configuration_create(CentaurConfiguration_t * o_config);
+
+/**
+ * Scom all of the centaurs with the same SCOM address.
+ * @param[in] The CentaurConfig object
+ * @param[in] The SCOM address
+ * @param[out] The array of data collected. Must be large enough to hold
+ * uint64_t data from each centaur.
+ * @return [0 | return code]
+ */
+int centaur_get_scom_vector(CentaurConfiguration_t* i_config,
+ uint32_t i_scom_address,
+ uint64_t* o_data);
+
+/**
+ * Scom one or more centaurs
+ * @param[in] The CentaurConfig object
+ * @param[in/out] The Centaur Scom Parms object
+ * @return The return code is part of the Centaur Scom Parms object
+ */
+void gpe_scom_centaur(CentaurConfiguration_t* i_config,
+ CentaurScomParms_t* i_parms);
+
+
+/**
+ * Collect the centaur thermal data
+ * @param[in] The CentaurConfig object
+ * @param[in/out] The Centaur data parm object
+ * @return [0 | return code]
+ */
+int centaur_get_mem_data(CentaurConfiguration_t* i_config,
+ CentaurGetMemDataParms_t* i_parms);
+
+#endif
diff --git a/src/occ_gpe1/gpe_centaur_configuration.c b/src/occ_gpe1/gpe_centaur_configuration.c
new file mode 100644
index 0000000..83ac500
--- /dev/null
+++ b/src/occ_gpe1/gpe_centaur_configuration.c
@@ -0,0 +1,538 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/procedures/lib/pm/centaur_thermal_access.c $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+/**
+ * @briefcentaur_thermal_access
+ */
+
+#include "gpe_centaur.h"
+#include "ppe42_scom.h"
+#include "pk.h"
+#include "p9_misc_scom_addresses.h"
+#include "mcs_firmware_registers.h"
+#include "pba_firmware_constants.h"
+#include "pba_register_addresses.h"
+#include "centaur_register_addresses.h"
+#include "ppe42_msr.h"
+#include "occhw_pba_common.h"
+
+// Which GPE controls the PBASLAVE
+#define OCI_MASTER_ID_GPE1 1
+
+// Power Bus Address bit that configures centaur for HOST/OCC P9=bit(38)
+#define PBA_HOST_OCC_CFG 0x0000000002000000ull;
+
+
+const uint32_t MCFGPR[OCCHW_NCENTAUR] =
+{
+ MCS_0_MCRSVDE,
+ MCS_0_MCRSVDF,
+ MCS_1_MCRSVDE,
+ MCS_1_MCRSVDF,
+ MCS_2_MCRSVDE,
+ MCS_2_MCRSVDF,
+ MCS_3_MCRSVDE,
+ MCS_3_MCRSVDF
+};
+
+//const uint32_t MCSMODE0[OCCHW_NCENTAUR / 2] __attribute__((section(".sdata2"))) =
+//{
+// MCS_0_MCMODE0,
+// MCS_1_MCMODE0,
+// MCS_2_MCMODE0,
+// MCS_3_MCMODE0
+//};
+
+//const uint32_t MCFIR[OCCHW_NCENTAUR / 2] __attribute((section(".sdata2"))) =
+//{
+// MCS_0_MCFIR,
+// MCS_1_MCFIR,
+// MCS_2_MCFIR,
+// MCS_3_MCFIR
+//};
+
+const uint32_t MCFGP[OCCHW_NCENTAUR/2] =
+{
+ MCS_0_MCFGP,
+ MCS_1_MCFGP,
+ MCS_2_MCFGP,
+ MCS_3_MCFGP
+};
+
+///////////////////////////////////////////////////////////////
+// These are PPE specific PBA routines.
+//////////////////////////////////////////////////////////////
+int
+gpe_pba_parms_create(GpePbaParms* parms,
+ int slave,
+ int write_ttype,
+ int write_tsize,
+ int read_ttype)
+{
+ pba_slvctln_t* slvctl, *mask;
+ pba_slvrst_t* slvrst;
+ pba_slvrst_t* slvrst_in_progress;
+ uint64_t all1 = 0xffffffffffffffffull;
+
+ parms->slave_id = slave;
+
+ slvctl = &(parms->slvctl);
+ mask = &(parms->mask);
+ slvrst = &(parms->slvrst);
+ slvrst_in_progress = &(parms->slvrst_in_progress);
+
+ parms->slvctl_address = PBA_SLVCTLN(slave);
+
+ slvrst->value = 0;
+ slvrst->fields.set = PBA_SLVRST_SET(slave);
+
+ slvrst_in_progress->value = 0;
+ slvrst_in_progress->fields.in_prog = PBA_SLVRST_IN_PROG(slave);
+
+ slvctl->value = 0;
+ mask->value = 0;
+
+ slvctl->fields.enable = 1;
+ mask->fields.enable = all1;
+
+ slvctl->fields.mid_match_value = OCI_MASTER_ID_GPE1;
+ mask->fields.mid_match_value = all1;
+
+ slvctl->fields.mid_care_mask = all1;
+ mask->fields.mid_care_mask = all1;
+
+ slvctl->fields.write_ttype = write_ttype;
+ mask->fields.write_ttype = all1;
+
+ slvctl->fields.write_tsize = write_tsize;
+ mask->fields.write_tsize = all1;
+
+ slvctl->fields.read_ttype = read_ttype;
+ mask->fields.read_ttype = all1;
+
+ slvctl->fields.buf_alloc_a = 1;
+ slvctl->fields.buf_alloc_b = 1;
+ slvctl->fields.buf_alloc_c = 1;
+ slvctl->fields.buf_alloc_w = 1;
+ mask->fields.buf_alloc_a = 1;
+ mask->fields.buf_alloc_b = 1;
+ mask->fields.buf_alloc_c = 1;
+ mask->fields.buf_alloc_w = 1;
+
+ if (read_ttype == PBA_READ_TTYPE_CI_PR_RD)
+ {
+
+ slvctl->fields.buf_invalidate_ctl = 1;
+ mask->fields.buf_invalidate_ctl = all1;
+
+ slvctl->fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
+ mask->fields.read_prefetch_ctl = all1;
+
+ }
+ else
+ {
+
+ slvctl->fields.buf_invalidate_ctl = 0;
+ mask->fields.buf_invalidate_ctl = all1;
+ }
+
+ mask->value = ~(mask->value);
+
+ return 0;
+}
+
+
+////////////////////////////////////////////////
+// Centaur specific routines
+////////////////////////////////////////////////
+int gpe_centaur_configuration_create(CentaurConfiguration_t* o_config)
+{
+ int rc = 0;
+ unsigned int i = 0;
+ mcfgpr_t mcfgpr;
+ // mcifir_t mcifir;
+ // mcsmode0_t mcsmode0;
+ pba_slvctln_t slvctl;
+ int designatedSync = -1;
+ uint64_t bar = 0;
+ uint64_t mask = 0;
+ uint64_t base = 0;
+ uint64_t* ptr = (uint64_t*)o_config;
+
+ // Prevent unwanted interrupts from scom errors
+ const uint32_t orig_msr = mfmsr() & MSR_SEM;
+ mtmsr((orig_msr & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM);
+
+ for(i = 0; i < sizeof(CentaurConfiguration_t) / 8; ++i)
+ {
+ *ptr++ = 0ull;
+ }
+
+ o_config->configRc = CENTAUR_NOT_CONFIGURED;
+
+ do
+ {
+ // Create the setups for the GPE procedures. The 'dataParms' are the
+ // setup for accessing the Centaur sensor cache. The 'scomParms' are
+ // the setup for accessing Centaur SCOMs.
+
+ rc = gpe_pba_parms_create(&(o_config->dataParms),
+ PBA_SLAVE_CENTAUR,
+ PBA_WRITE_TTYPE_CI_PR_W,
+ PBA_WRITE_TTYPE_DC,
+ PBA_READ_TTYPE_CL_RD_NC);
+
+ if (rc)
+ {
+ rc = CENTAUR_DATA_SETUP_ERROR;
+ break;
+ }
+
+ rc = gpe_pba_parms_create(&(o_config->scomParms),
+ PBA_SLAVE_CENTAUR,
+ PBA_WRITE_TTYPE_CI_PR_W,
+ PBA_WRITE_TTYPE_DC,
+ PBA_READ_TTYPE_CI_PR_RD);
+
+ if (rc)
+ {
+ rc = CENTAUR_SCOM_SETUP_ERROR;
+ break;
+ }
+
+ // Go into each MCS on the chip, and for all enabled MCS get a couple
+ // of SCOMs and check configuration items for correctness. If any of
+ // the Centaur are configured, exactly one of the MCS must be
+ // designated to receive the SYNC commands.
+
+ // Note that the code uniformly treats SCOM failures of the MCFGPR
+ // registers as an unconfigured Centaur. This works both for Murano,
+ // which only defines the final 4 MCS, as well as for our VBU models
+ // where some of the "valid" MCS are not in the simulation models.
+
+ for (i = 0; i < OCCHW_NCENTAUR; ++i)
+ {
+ uint64_t val64;
+
+ // If can't scom then assume not configured
+ //rc = getscom_abs(MCFIR[i / 2], &(mcifir.value));
+
+ //if (rc)
+ //{
+ // rc = 0;
+ // continue;
+ //}
+
+ // See Cumulus MC "Datapath Fault Isolation Register" Is it right???
+ //FIR bits have changed from p8 TODO do we need to look at the fir
+ //for P9 ??
+ //if (mcifir.fields.channel_fail_signal_active)
+ //{
+ // continue;
+ //}
+
+ // Routine p9c_set_inband_addr.C uses MCRSVDE and MCRSVDF to set
+ // inband address (MCFGPR)
+ //
+ rc = getscom_abs(MCFGPR[i], &(mcfgpr.value));
+
+ if (rc)
+ {
+ rc = 0;
+ continue;
+ }
+
+ // TODO ENGD work-around until gets pushed up.
+ // Turn on bit 25 in mode0 regs. They should all have the same value
+ rc = getscom_abs(0x05010811, &val64);
+ val64 |= 0x0000004000000000ull;
+ rc = putscom_abs(0x05010811, val64);
+ rc = putscom_abs(0x05010891, val64);
+ rc = putscom_abs(0x03010811, val64);
+ rc = putscom_abs(0x03010891, val64);
+
+ // If inband scom is not configured then assume the centaur does not exist
+ if (!mcfgpr.fields.mcfgprq_valid)
+ {
+ continue;
+ }
+
+
+ // The 31-bit base-address is moved to begin at bit 8 in the
+ // 64-bit PowerBus address.
+ // Set the HOST/OCC bit in the address.
+ o_config->baseAddress[i] =
+ ((uint64_t)(mcfgpr.fields.mcfgprq_base_address) << 25) | PBA_HOST_OCC_CFG;
+
+ PK_TRACE_DBG("Centar[%d] Base Address: %016llx",i,o_config->baseAddress[i]);
+
+
+ // TODO this bit no longer exists
+ // If this MCS is configured to be the designated SYNC unit, it
+ // must be the only one.
+
+ //if (mcsmode0.fields.enable_centaur_sync)
+ //{
+ // if (designatedSync > 0)
+ // {
+ // PK_TRACE_DBG("Both MCS %d and %d are designated "
+ // "for Centaur Sync",
+ // designatedSync, i);
+ // rc = CENTAUR_MULTIPLE_DESIGNATED_SYNC;
+ // break;
+
+ // }
+ // else
+ // {
+ // designatedSync = i;
+ // }
+ //}
+
+
+ // Add the Centaur to the configuration
+ o_config->config |= (CHIP_CONFIG_MCS(i) | CHIP_CONFIG_CENTAUR(i));
+ }
+
+ if (rc)
+ {
+ break;
+ }
+
+
+ // In p9 the enable_centaur_sync is no longer available as a mode bit.
+ // TODO Anything to do?
+ // P8:
+ // If Centaur are configured, make sure at least one of the MCS will
+ // handle the SYNC. If so, convert its base address into an address
+ // for issuing SYNC commands by setting bits 27 (OCC) 28 and 29
+ // (Sync), then insert this address into the extended address field of
+ // a PBA slave control register image. gsc_scom_centaur() then merges
+ // this extended address into the PBA slave control register (which
+ // has been set up for Centaur SCOM) to do the SYNC.
+
+ // In the override mode (i_setup > 1) we tag the first valid MCS
+ // to recieve the sync if the firmware has not set it up correctly.
+
+ if (o_config->config)
+ {
+#if defined(__P8_DESIGNATED_SYNC__)
+
+ if (designatedSync < 0)
+ {
+ if (i_setup <= 1)
+ {
+ PK_TRACE_DBG("No MCS is designated for Centaur SYNC");
+ rc = CENTAUR_NO_DESIGNATED_SYNC;
+ break;
+
+ }
+ else
+ {
+
+ designatedSync =
+ cntlz32(o_config->config << CHIP_CONFIG_MCS_BASE);
+
+ rc = _getscom(designatedSync, MCSMODE0, &(mcsmode0.value));
+
+ if (rc)
+ {
+ PK_TRACE_DBG("Unexpected rc = 0x%08x "
+ "SCOMing MCSMODE0(%d)",
+ (uint32_t)rc,
+ designatedSync);
+
+ rc = CENTAUR_MCSMODE0_SCOM_FAILURE;
+ break;
+ }
+
+ mcsmode0.fields.enable_centaur_sync = 1;
+
+ rc = _putscom(designatedSync, MCSMODE0, mcsmode0.value);
+
+ if (rc)
+ {
+ PK_TRACE_DBG("Unexpected rc = 0x%08x "
+ "SCOMing MCSMODE0(%d)",
+ (uint32_t)rc,
+ designatedSync);
+
+ rc = CENTAUR_MCSMODE0_SCOM_FAILURE;
+ break;
+ }
+ }
+ }
+
+#else
+ // first centaur found
+ designatedSync = cntlz32(o_config->config << CHIP_CONFIG_MCS_BASE);
+#endif
+ // Set the OCC/HOST bit in the PBA
+ base = o_config->baseAddress[designatedSync] | PBA_HOST_OCC_CFG;
+
+ //Pick out the PBA address sub field that will be set by the slvctl extaddr
+ //bits [23:36]
+ slvctl.value = 0;
+ slvctl.fields.extaddr = base >> 27;
+
+ o_config->syncSlaveControl.value = slvctl.value;
+ }
+
+
+ // Configure the PBA BAR and PBA BARMSK.
+ // Set the BARMSK bits such that:
+ // -PBA[8:22] are provided by the PBABAR.
+ // -PBA[23:36] are provided by the PBASLVCTL ExtrAddr field
+ // -PBA[37:43] are provided by the OCI addr[5:11]
+ // PBA[44:63] will always come from the OCI addr[12:31]
+ // Note: This code should no longer be needed when the BAR/BARMSK is set
+ // by PHYP.
+ if (o_config->config != 0)
+ {
+ uint64_t bar = 0;
+ uint64_t barMsk = PBA_BARMSKN_MASK_MASK;
+
+ for (i = 0; i < OCCHW_NCENTAUR; ++i)
+ {
+ bar |= o_config->baseAddress[i];
+ }
+
+ bar &= ~barMsk;
+
+ PK_TRACE_DBG("PBABAR(%d): %016llx", PBA_BAR_CENTAUR, bar);
+ PK_TRACE_DBG("PBABARMSK: %016llx", barMsk);
+
+ rc = putscom_abs(PBA_BARMSKN(PBA_BAR_CENTAUR), barMsk);
+
+ if (rc)
+ {
+ PK_TRACE_DBG("Unexpected rc = 0x%08x SCOMing PBA_BARMSKN(%d)\n",
+ (uint32_t)rc, PBA_BAR_CENTAUR);
+ rc = CENTAUR_BARMSKN_PUTSCOM_FAILURE;
+ break;
+ }
+
+ rc = putscom_abs(PBA_BARN(PBA_BAR_CENTAUR), bar);
+ if (rc)
+ {
+ PK_TRACE_DBG("Unexpected rc = 0x%08x SCOMing PBA_BARN(%d)\n",
+ (uint32_t)rc, PBA_BAR_CENTAUR);
+ rc = CENTAUR_BARN_PUTSCOM_FAILURE;
+ break;
+ }
+ }
+
+ // Do an independent check that every Centaur base address
+ // can be generated by the combination of the current BAR and
+ // BAR Mask, along with the initial requirement that the mask must
+ // include at least bits 38:43.
+
+ if (o_config->config != 0)
+ {
+ rc = getscom_abs(PBA_BARN(PBA_BAR_CENTAUR), &bar);
+
+ if (rc)
+ {
+ PK_TRACE_DBG("Unexpected rc = 0x%08x SCOMing PBA_BARN(%d)\n",
+ (uint32_t)rc, PBA_BAR_CENTAUR);
+ rc = CENTAUR_BARN_GETSCOM_FAILURE;
+ break;
+ }
+
+ rc = getscom_abs(PBA_BARMSKN(PBA_BAR_CENTAUR), &mask);
+
+ if (rc)
+ {
+ PK_TRACE_DBG("Unexpected rc = 0x%08x SCOMing PBA_BARMSKN(%d)\n",
+ (uint32_t)rc, PBA_BAR_CENTAUR);
+ rc = CENTAUR_BARMSKN_GETSCOM_FAILURE;
+ break;
+ }
+
+ bar = bar & PBA_BARN_ADDR_MASK;
+ mask = mask & PBA_BARMSKN_MASK_MASK;
+
+ if ((mask & 0x0000000003f00000ull) != 0x0000000003f00000ull)
+ {
+
+ PK_TRACE("PBA BAR mask (%d) does not cover bits 38:43\n", PBA_BAR_CENTAUR);
+ rc = CENTAUR_MASK_ERROR;
+ break;
+ }
+
+ for (i = 0; i < OCCHW_NCENTAUR; ++i)
+ {
+ if (o_config->baseAddress[i] != 0)
+ {
+ if ((o_config->baseAddress[i] & ~mask) !=
+ (bar & ~mask))
+ {
+
+ PK_TRACE("BAR/Mask (%d) error for MCS/Centaur %d",
+ PBA_BAR_CENTAUR, i);
+
+ PK_TRACE(" base = 0x%08x%08x",
+ (uint32_t)(o_config->baseAddress[i]>>32),
+ (uint32_t)(o_config->baseAddress[i]));
+
+ PK_TRACE(" bar = 0x%08x%08x"
+ " mask = 0x%08x%08x",
+ (uint32_t)(bar >> 32),
+ (uint32_t)(bar),
+ (uint32_t)(mask >> 32),
+ (uint32_t)(mask));
+
+ rc = CENTAUR_BAR_MASK_ERROR;
+ break;
+ }
+ }
+ }
+
+ if (rc)
+ {
+ break;
+ }
+ }
+
+
+ // At this point the structure is initialized well-enough that it can
+ // be used by gpe_scom_centaur().
+
+
+ o_config->configRc = 0;
+
+ if (o_config->config == 0)
+ {
+ break;
+ }
+
+
+ // Get Device ID from each centaur
+ centaur_get_scom_vector(o_config,
+ CENTAUR_DEVICE_ID,
+ (uint64_t*)(&(o_config->deviceId[0])));
+
+ }
+ while(0);
+
+ o_config->configRc = rc;
+
+ mtmsr(orig_msr);
+
+ return rc;
+}
+
diff --git a/src/occ_gpe1/gpe_centaur_scom.c b/src/occ_gpe1/gpe_centaur_scom.c
new file mode 100644
index 0000000..cef0977
--- /dev/null
+++ b/src/occ_gpe1/gpe_centaur_scom.c
@@ -0,0 +1,571 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: chips/p9/procedures/lib/pm/centaur_scom.c $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* EKB Project */
+/* */
+/* COPYRIGHT 2017 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* IBM_PROLOG_END_TAG */
+#include <stdint.h>
+#include "gpe_centaur.h"
+#include "gpe_pba_cntl.h"
+#include "ppe42_scom.h"
+#include "ppe42.h"
+#include "pba_register_addresses.h"
+#include "ppe42_msr.h"
+
+/**
+ * @file centaur_scom
+ * @brief scom access from gpe to a centaur
+ */
+
+/**
+ * Setup the PBASLVCTLN extended address and calculate the OCI scom address
+ * @param[in] PBA base address
+ * @param[in] The Centaur scom address
+ * @returns the OCI address to scom the centaur
+ * @Post The extended address field in the PBASLVCNT is set
+ */
+uint32_t centaur_scom_setup(CentaurConfiguration_t* i_config,
+ uint32_t i_centaur_instance,
+ uint32_t i_scom_address)
+{
+ uint32_t oci_addr = 0;
+ #if defined(__PBASLV__)
+ pba_slvctln_t slvctln;
+#endif
+ uint64_t pb_addr = i_config->baseAddress[i_centaur_instance];
+
+ // Break address into componets
+ uint32_t local = i_scom_address & 0x00001fff;
+ uint32_t port = i_scom_address & 0x000f0000;
+ uint32_t slave = i_scom_address & 0x03000000;
+ uint32_t multi = i_scom_address & 0xc0000000;
+
+ // compress to 21 bits for P9
+ uint32_t scom_address =
+ local +
+ (port >> 3) +
+ (slave >> 7) +
+ (multi >> 11);
+
+ // P9: Turn on bit 38 to indicate OCC
+ pb_addr |= 0x0000000002000000ull;
+ pb_addr |= ((uint64_t)scom_address << 3);
+
+ #if defined(__PBASLV__)
+ // put bits 23:36 of address into slvctln extended addr
+ PPE_LVD((i_config->scomParms).slvctl_address, slvctln.value);
+ slvctln.fields.extaddr = pb_addr >> 27;
+ PPE_STVD((i_config->scomParms).slvctl_address, slvctln.value);
+#endif
+ // HW bug work-around
+ {
+ // workaround - don't use extr addr - use pbabar.
+ uint64_t barMsk = 0;
+ // put the PBA in the BAR
+ putscom_abs(PBA_BARN(PBA_BAR_CENTAUR), pb_addr);
+ putscom_abs(PBA_BARMSKN(PBA_BAR_CENTAUR), barMsk);
+ }
+ // make oci address
+ oci_addr = (uint32_t)(pb_addr & 0x07ffffffull);
+
+ // upper nibble is PBA region and BAR_SELECT
+ oci_addr |= ((PBA_BAR_CENTAUR | 0x8) << 28);
+ PK_TRACE_DBG("Centaur OCI scom addr: %08x",oci_addr);
+ return oci_addr;
+}
+
+uint32_t centaur_sensorcache_setup(CentaurConfiguration_t* i_config,
+ uint32_t i_centaur_instance)
+{
+ uint32_t oci_addr = 0;
+#if defined(__PBASLV__)
+ pba_slvctln_t slvctln;
+#endif
+ uint64_t pb_addr = i_config->baseAddress[i_centaur_instance];
+
+ // bit 38 set OCI master, bits 39,40 Centaur thermal sensors '10'b
+ pb_addr |= 0x0000000003000000ull;
+
+#if defined(__PBASLV__)
+ PPE_LVD((i_config->dataParms).slvctl_address, slvctln.value);
+ slvctln.fields.extaddr = pb_addr >> 27;
+ PPE_STVD((i_config->dataParms).slvctl_address, slvctln.value);
+#endif
+ {
+ // HW bug workaround - don't use extr addr - use pbabar.
+ uint64_t barMsk = 0;
+ // put the PBA in the BAR
+ putscom_abs(PBA_BARN(PBA_BAR_CENTAUR), pb_addr);
+ putscom_abs(PBA_BARMSKN(PBA_BAR_CENTAUR), barMsk);
+ }
+ // make oci address
+ oci_addr = (uint32_t)(pb_addr & 0x07ffffffull);
+
+ // PBA space bits[0:1] = '10' bar select bits[3:4]
+ oci_addr |= ((PBA_BAR_CENTAUR | 0x8) << 28);
+
+ return oci_addr;
+}
+
+void pbaslvctl_reset(GpePbaParms* i_pba_parms)
+{
+ uint64_t val = 0;
+
+ do
+ {
+ PPE_STVD(PBA_SLVRST, i_pba_parms->slvrst.value);
+ PPE_LVD(PBA_SLVRST, val);
+ val &= i_pba_parms->slvrst_in_progress.value;
+ }
+ while(val != 0);
+}
+
+uint64_t pbaslvctl_setup(GpePbaParms* i_pba_parms)
+{
+ uint64_t slvctl_val;
+ uint64_t slvctl_val_org;
+ PPE_LVD(i_pba_parms->slvctl_address, slvctl_val_org);
+ slvctl_val = slvctl_val_org;
+ slvctl_val &= i_pba_parms->mask.value;
+ slvctl_val |= i_pba_parms->slvctl.value;
+ PPE_STVD(i_pba_parms->slvctl_address, slvctl_val);
+ return slvctl_val_org;
+}
+
+// Get the most severe rc from the sibrca field in the msr
+int rc_from_sibrc()
+{
+ int rc = 0;
+ uint32_t sibrca = (mfmsr() & 0x0000007f);
+ if(sibrca)
+ {
+ uint32_t mask = 1;
+ rc = 7;
+ for(; mask != 0x00000080; mask <<=1)
+ {
+ if( mask & sibrca )
+ {
+ break;
+ }
+ --rc;
+ }
+ }
+ return rc;
+}
+
+// Get data from each existing centaur.
+int centaur_get_scom_vector(CentaurConfiguration_t* i_config,
+ uint32_t i_scom_address,
+ uint64_t* o_data)
+{
+ int instance = 0;
+ uint64_t pba_slvctln_save;
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
+
+ // clear SIB errors in MSR
+ mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)));
+
+ for(instance = 0; instance < OCCHW_NCENTAUR; ++instance)
+ {
+ if( CHIP_CONFIG_CENTAUR(instance) & (i_config->config))
+ {
+ uint32_t oci_addr =
+ centaur_scom_setup(i_config, instance, i_scom_address);
+
+ // read centaur scom
+ PPE_LVD(oci_addr, *o_data);
+ }
+ else
+ {
+ *o_data = 0;
+ }
+
+ ++o_data;
+ }
+
+ // gpe_pba_cntl function?
+ pbaslvctl_reset(&(i_config->scomParms));
+ PPE_STVD((i_config->scomParms).slvctl_address, pba_slvctln_save);
+
+ return rc_from_sibrc();
+}
+
+int centaur_get_scom(CentaurConfiguration_t* i_config,
+ int i_centaur_instance,
+ uint32_t i_scom_address,
+ uint64_t* o_data)
+{
+ int rc = 0;
+ uint32_t oci_addr;
+ uint64_t pba_slvctln_save;
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
+
+ oci_addr =
+ centaur_scom_setup(i_config, i_centaur_instance, i_scom_address);
+
+ if( CHIP_CONFIG_CENTAUR(i_centaur_instance) & (i_config->config))
+ {
+ // read centaur scom
+ rc = getscom_abs(oci_addr, o_data);
+ }
+ else
+ {
+ *o_data = 0;
+ }
+
+ // gpe_pba_cntl function?
+ pbaslvctl_reset(&(i_config->scomParms));
+ PPE_STVD((i_config->scomParms).slvctl_address, pba_slvctln_save);
+
+ return rc;
+}
+
+
+// Write all configured centaur with the same data
+int centaur_put_scom_all(CentaurConfiguration_t* i_config,
+ uint32_t i_scom_address,
+ uint64_t i_data)
+{
+ int instance = 0;
+ uint64_t pba_slvctln_save;
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
+
+ // clear SIB errors in MSR
+ mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)));
+
+ for(instance = 0; instance < OCCHW_NCENTAUR; ++instance)
+ {
+ if( CHIP_CONFIG_CENTAUR(instance) & (i_config->config))
+ {
+ uint32_t oci_addr =
+ centaur_scom_setup(i_config, instance, i_scom_address);
+
+ // centaur scom
+ PPE_STVD(oci_addr, i_data);
+ }
+ }
+
+ // gpe_pba_cntl function?
+ pbaslvctl_reset(&(i_config->scomParms));
+ PPE_STVD((i_config->scomParms).slvctl_address, pba_slvctln_save);
+
+ return rc_from_sibrc();
+}
+
+int centaur_put_scom(CentaurConfiguration_t* i_config,
+ int i_centaur_instance,
+ uint32_t i_scom_address,
+ uint64_t i_data)
+{
+ int rc = 0;
+ uint32_t oci_addr;
+ uint64_t pba_slvctln_save;
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
+
+ oci_addr =
+ centaur_scom_setup(i_config, i_centaur_instance, i_scom_address);
+
+ if( CHIP_CONFIG_CENTAUR(i_centaur_instance) & (i_config->config))
+ {
+ // write centaur scom
+ rc = putscom_abs(oci_addr, i_data);
+ }
+ else
+ {
+ rc = CENTAUR_INVALID_SCOM;
+ }
+
+ // gpe_pba_cntl function?
+ pbaslvctl_reset(&(i_config->scomParms));
+ PPE_STVD((i_config->scomParms).slvctl_address, pba_slvctln_save);
+
+ return rc;
+}
+
+// write x
+int centaur_scom_rmw(CentaurConfiguration_t* i_config,
+ int i_centaur_instance,
+ uint32_t i_scom_address,
+ uint64_t i_mask,
+ uint64_t* i_data)
+{
+ int rc = 0;
+ uint32_t oci_addr;
+ uint64_t pba_slvctln_save;
+ uint64_t data64;
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
+
+ oci_addr =
+ centaur_scom_setup(i_config, i_centaur_instance, i_scom_address);
+
+ rc = getscom_abs(oci_addr, &data64);
+ if(!rc)
+ {
+ data64 &= (i_mask ^ 0xffffffffffffffffull);
+ data64 |= *i_data;
+
+ rc = putscom_abs(oci_addr, data64);
+ if(i_scom_address == 0x3010416)
+ {
+ PK_TRACE("N/M RMW PUTSCOM: %08x%08x",(uint32_t)(data64>>32),(uint32_t)data64);
+ }
+ }
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ PPE_STVD((i_config->scomParms).slvctl_address, pba_slvctln_save);
+
+ return rc;
+}
+
+
+int centaur_scom_rmw_all(CentaurConfiguration_t* i_config,
+ uint32_t i_scom_address,
+ uint64_t i_mask,
+ uint64_t i_data)
+{
+ int instance = 0;
+ uint64_t pba_slvctln_save;
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
+
+ // clear SIB errors in MSR
+ mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)));
+
+ for(instance = 0; (instance < OCCHW_NCENTAUR); ++instance)
+ {
+ if( CHIP_CONFIG_CENTAUR(instance) & (i_config->config))
+ {
+ uint64_t data64;
+ uint32_t oci_addr =
+ centaur_scom_setup(i_config, instance, i_scom_address);
+
+ PPE_LVD(oci_addr, data64);
+ data64 &= (i_mask ^ 0xffffffffffffffffull);
+ data64 |= i_data;
+ PPE_STVD(oci_addr, data64);
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ }
+ }
+
+ PPE_STVD((i_config->scomParms).slvctl_address, pba_slvctln_save);
+
+ return rc_from_sibrc();
+}
+
+
+int centaur_scom_sync(CentaurConfiguration_t* i_config,
+ uint64_t i_data)
+{
+ int rc = 0;
+ uint32_t addr = (PBA_BAR_CENTAUR << 28);
+ uint64_t pba_slvctln_save;
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->scomParms));
+
+ // sync setup
+ pba_slvctln_t slvctl;
+ PPE_LVD((i_config->scomParms).slvctl_address, slvctl.value);
+ slvctl.fields.extaddr = (i_config->syncSlaveControl).fields.extaddr;
+ PPE_STVD((i_config->scomParms).slvctl_address, slvctl.value);
+
+ PPE_STVD(addr, i_data);
+
+ pbaslvctl_reset(&(i_config->scomParms));
+ PPE_STVD((i_config->scomParms).slvctl_address, pba_slvctln_save);
+
+ return rc;
+}
+
+
+int centaur_scom_sync_all(CentaurConfiguration_t* i_config,
+ uint64_t i_data)
+{
+ return centaur_scom_sync(i_config,
+ (uint64_t)(i_config->config << 24) | i_data);
+}
+
+// read centaur data sensor cache
+int centaur_get_mem_data(CentaurConfiguration_t* i_config,
+ CentaurGetMemDataParms_t* i_parms)
+{
+ int rc = 0;
+ uint32_t oci_addr = 0;
+ uint64_t pba_slvctln_save;
+ uint64_t data64 = 0;
+ uint64_t barMskOrg = 0;
+
+ i_parms->error.rc = CENTAUR_GET_MEM_DATA_DIED;
+
+ // HW bug work-around
+ rc = getscom_abs(PBA_BARMSKN(PBA_BAR_CENTAUR), &barMskOrg);
+ if(rc)
+ {
+ PK_TRACE("Workaround failed to read bar mask. rc = %x",rc);
+ }
+
+ pbaslvctl_reset(&(i_config->dataParms));
+ pba_slvctln_save = pbaslvctl_setup(&(i_config->dataParms));
+
+ if(i_parms->collect != -1)
+ {
+ if((i_parms->collect >= OCCHW_NCENTAUR) ||
+ (0 == (CHIP_CONFIG_CENTAUR(i_parms->collect) & (i_config->config))))
+ {
+ rc = CENTAUR_GET_MEM_DATA_COLLECT_INVALID;
+ }
+ else
+ {
+ oci_addr = centaur_sensorcache_setup(i_config, i_parms->collect);
+
+ // Poke the Centaur sensor cache by writing to base address.
+ data64 = 0;
+ PPE_STVD(oci_addr, data64);
+
+ // Read 128 bytes from centaur cache
+ int i;
+ for(i = 0; i < 128; i += 8)
+ {
+ PPE_LVDX(oci_addr, i, data64);
+ PPE_STVDX((i_parms->data), i, data64);
+ }
+ }
+ }
+ // TODO Decide to keep this or not.
+#if defined(__JUNK__)
+ if(!rc && i_parms->update != -1)
+ {
+ if((i_parms->update >= OCCHW_NCENTAUR) ||
+ (0 == (CHIP_CONFIG_CENTAUR(i_parms->update) & (i_config->config))))
+ {
+ rc = CENTAUR_GET_MEM_DATA_UPDATE_INVALID;
+ }
+ else
+ {
+ oci_addr = centaur_sensorcache_setup(i_config, i_parms->update);
+
+ //PK_TRACE("CACHE POKE: %08x",oci_addr);
+ // Writing a zero to this address "pokes" the centaur.
+ data64 = 0;
+ PPE_STVD(oci_addr, data64);
+ }
+ }
+#endif
+
+ pbaslvctl_reset(&(i_config->dataParms));
+ PPE_STVD((i_config->dataParms).slvctl_address, pba_slvctln_save);
+
+ // TODO if RC then check for centaur channel checkstop
+ // The MCFIR reg no longer contains a bit for CHANNEL_FAIL_SIGNAL_ACTIVE.
+ // No equivalent has been identified yet for P9.
+ // Return rc = CENTAUR_CHANNEL_CHECKSTOP
+
+ // HW bug work-around
+ rc = putscom_abs(PBA_BARMSKN(PBA_BAR_CENTAUR), barMskOrg);
+ if(rc)
+ {
+ PK_TRACE("Work around Failed to set bar mask. rc = %x",rc);
+ }
+
+ i_parms->error.rc = rc;
+ return rc;
+}
+
+
+// CentaurConfiguration needs to be setup before this is called
+
+void gpe_scom_centaur(CentaurConfiguration_t* i_config,
+ CentaurScomParms_t* i_parms)
+{
+ int i;
+ mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM);
+
+ // Do reset and pba_setup here?
+ for(i = 0; i < i_parms->entries; ++i)
+ {
+ switch(i_parms->scomList[i].commandType)
+ {
+ case CENTAUR_SCOM_NOP:
+ break;
+
+ case CENTAUR_SCOM_READ:
+ centaur_get_scom(i_config,
+ i_parms->scomList[i].instanceNumber,
+ i_parms->scomList[i].scom,
+ &(i_parms->scomList[i].data));
+ break;
+
+ case CENTAUR_SCOM_WRITE:
+ centaur_put_scom(i_config,
+ i_parms->scomList[i].instanceNumber,
+ i_parms->scomList[i].scom,
+ i_parms->scomList[i].data);
+ break;
+
+ case CENTAUR_SCOM_RMW:
+ centaur_scom_rmw(i_config,
+ i_parms->scomList[i].instanceNumber,
+ i_parms->scomList[i].scom,
+ i_parms->scomList[i].mask,
+ &(i_parms->scomList[i].data));
+ break;
+
+ case CENTAUR_SCOM_READ_VECTOR:
+ centaur_get_scom_vector(i_config,
+ i_parms->scomList[i].scom,
+ i_parms->scomList[i].pData
+ );
+ break;
+
+ case CENTAUR_SCOM_WRITE_ALL:
+ centaur_put_scom_all(i_config,
+ i_parms->scomList[i].scom,
+ i_parms->scomList[i].data);
+ break;
+
+ case CENTAUR_SCOM_RMW_ALL:
+ centaur_scom_rmw_all(i_config,
+ i_parms->scomList[i].scom,
+ i_parms->scomList[i].mask,
+ i_parms->scomList[i].data);
+ break;
+
+ case CENTAUR_SCOM_CENTAUR_SYNC:
+ centaur_scom_sync(i_config,
+ i_parms->scomList[i].data);
+ break;
+
+ case CENTAUR_SCOM_CENTAUR_SYNC_ALL:
+ centaur_scom_sync(i_config,
+ i_parms->scomList[i].data);
+ break;
+
+ default:
+ break;
+ };
+ }
+}
diff --git a/src/occ_gpe1/img_defs.mk b/src/occ_gpe1/img_defs.mk
index ba8cc18..be5c5a3 100644
--- a/src/occ_gpe1/img_defs.mk
+++ b/src/occ_gpe1/img_defs.mk
@@ -94,6 +94,10 @@ ifndef PK_SRCDIR
export PK_SRCDIR = $(abspath ../ppe/pk)
endif
+ifndef OCCHW_SRCDIR
+export OCCHW_SRCDIR = $(abspath ../ssx/occhw)
+endif
+
ifndef COMMONLIB_SRCDIR
export COMMONLIB_SRCDIR = $(abspath ../lib/common)
endif
@@ -111,16 +115,11 @@ $(warning The CTEPATH variable is not defined; Defaulting to /afs/awd)
export CTEPATH = /afs/awd/projects/cte
endif
-ifdef P2P_ENABLE
-# TODO
-else
-
# libs needed by compiler
ifndef PPE_TOOL_PATH
PPE_TOOL_PATH = $(CTEPATH)/tools/ppetools/prod
LD_LIBRARY_PATH += :$(PPE_TOOL_PATH)/lib:
export LD_LIBRARY_PATH
-endif
ifndef GCC-TOOL-PREFIX
GCC-TOOL-PREFIX = $(PPE_TOOL_PATH)/bin/powerpc-eabi-
@@ -203,11 +202,19 @@ DEFS += $(GCC-DEFS)
############################################################################
-INCLUDES += $(IMG_INCLUDES) $(GLOBAL_INCLUDES) \
- -I$(PK_SRCDIR)/kernel -I$(PK_SRCDIR)/ppe42 -I$(PK_SRCDIR)/trace \
- -I$(PK_SRCDIR)/$(PPE_TYPE) -I$(PK_SRCDIR)/../../include \
- -I$(PK_SRCDIR)/../../include/registers -I$(OCCLIB_SRCDIR) -I$(COMMONLIB_SRCDIR) \
- -I$(OCC_COMMON_TYPES_DIR) -I$(IMAGE_SRCDIR)/../common
+INCLUDES += $(IMG_INCLUDES)
+INCLUDES += $(GLOBAL_INCLUDES)
+INCLUDES += -I$(PK_SRCDIR)/kernel
+INCLUDES += -I$(PK_SRCDIR)/ppe42
+INCLUDES += -I$(PK_SRCDIR)/trace
+INCLUDES += -I$(PK_SRCDIR)/$(PPE_TYPE)
+INCLUDES += -I$(PK_SRCDIR)/../../include
+INCLUDES += -I$(PK_SRCDIR)/../../include/registers
+INCLUDES += -I$(OCCLIB_SRCDIR)
+INCLUDES += -I$(COMMONLIB_SRCDIR)
+INCLUDES += -I$(OCC_COMMON_TYPES_DIR)
+INCLUDES += -I$(IMAGE_SRCDIR)/../common
+INCLUDES += -I$(OCCHW_SRCDIR)
ifdef P2P_ENABLE
PIPE-CFLAGS = -pipe -Wa,-m405
diff --git a/src/occ_gpe1/ipc_func_tables.c b/src/occ_gpe1/ipc_func_tables.c
index a7fe5ea..2ca2486 100644
--- a/src/occ_gpe1/ipc_func_tables.c
+++ b/src/occ_gpe1/ipc_func_tables.c
@@ -26,6 +26,7 @@
#include "ipc_async_cmd.h"
#include "gpe1_dimm.h"
#include "gpu_structs.h"
+#include "gpe_centaur.h"
void gpe_dimm_control(ipc_msg_t* cmd, void* arg);
void gpe1_nop(ipc_msg_t* cmd, void* arg);
@@ -84,9 +85,9 @@ IPC_HANDLER(gpe_24x7, 0) // 4 - IPC_ST_24_X_7_FUNCID
IPC_HANDLER(gpe_mem_power_control, 0) // 5 - IPC_ST_MEM_POWER_CONTROL_FUNCID
IPC_HANDLER(gpe_gpu_sm, 0) // 6 - IPC_ST_GPU_SM_FUNCID
IPC_HANDLER(gpe_gpu_init, 0) // 7 - IPC_ST_GPE_GPU_INIT_FUNCID
-IPC_HANDLER_DEFAULT // 8
-IPC_HANDLER_DEFAULT // 9
-IPC_HANDLER_DEFAULT // 10
+IPC_HANDLER(gpe_centaur_scom, 0) // 8 - IPC_ST_CENTAUR_SCOM_FUNCID
+IPC_HANDLER(gpe_centaur_data, 0) // 9 - IPC_ST_CENTAUR_DATA_FUNCID
+IPC_HANDLER(gpe_centaur_init, 0) // 10 -IPC_ST_CENTAUR_INIT_FUNCID
IPC_HANDLER_DEFAULT // 11
IPC_HANDLER_DEFAULT // 12
IPC_HANDLER_DEFAULT // 13
diff --git a/src/occ_gpe1/topfiles.mk b/src/occ_gpe1/topfiles.mk
index d0c2c2f..672d1f7 100644
--- a/src/occ_gpe1/topfiles.mk
+++ b/src/occ_gpe1/topfiles.mk
@@ -25,7 +25,8 @@
TOP-C-SOURCES = gpe1_main.c gpe1_dimm_read.c gpe1_dimm_reset.c nop.c \
pk_app_irq_table.c ipc_func_tables.c gpe1_dimm_control.c \
- gpe1_24x7.c gpe1_memory_power_control.c gpe_gpu_init.c
+ gpe1_24x7.c gpe1_memory_power_control.c gpe_gpu_init.c \
+ gpe_centaur_scom.c gpe_centaur_configuration.c gpe_centaur.c
TOP-S-SOURCES =
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