diff options
Diffstat (limited to 'src/occ_405')
| -rwxr-xr-x | src/occ_405/incl/occ_common.h | 7 | ||||
| -rwxr-xr-x | src/occ_405/main.c | 722 | ||||
| -rw-r--r-- | src/occ_405/occ_service_codes.h | 4 | ||||
| -rw-r--r-- | src/occ_405/pgpe/pgpe_shared.h | 72 | ||||
| -rwxr-xr-x | src/occ_405/ssx_app_cfg.h | 5 | ||||
| -rwxr-xr-x | src/occ_405/state.c | 57 | ||||
| -rwxr-xr-x | src/occ_405/timer/timer.c | 21 | ||||
| -rw-r--r-- | src/occ_405/wof/wof.c | 9 | ||||
| -rw-r--r-- | src/occ_405/wof/wof.h | 6 |
9 files changed, 504 insertions, 399 deletions
diff --git a/src/occ_405/incl/occ_common.h b/src/occ_405/incl/occ_common.h index eadcd95..626b744 100755 --- a/src/occ_405/incl/occ_common.h +++ b/src/occ_405/incl/occ_common.h @@ -261,8 +261,11 @@ enum NEST_DTS_INITIALIZED = 0x0700, CENTAUR_INITIALIZED = 0x07ff, SLAVE_OCC_INITIALIZED = 0x08ff, - PGPE_IMAGE_HEADER_READ = 0x094f, - PPMR_IMAGE_HEADER_READ = 0x098f, + READ_HCODE_HEADERS = 0x0900, + PPMR_IMAGE_HEADER_READ = 0x0910, + OPPB_IMAGE_HEADER_READ = 0x0920, + PGPE_IMAGE_HEADER_READ = 0x0930, + WOF_IMAGE_HEADER_READ = 0x0940, WATCHDOG_INITIALIZED = 0x09ff, RTL_TIMER_INITIALIZED = 0x0aff, SEMS_AND_TIMERS_INITIALIZED = 0x0bff, diff --git a/src/occ_405/main.c b/src/occ_405/main.c index 8cfac7e..035a9b6 100755 --- a/src/occ_405/main.c +++ b/src/occ_405/main.c @@ -75,8 +75,6 @@ extern apss_start_args_t G_gpe_start_pwr_meas_read_args; extern apss_continue_args_t G_gpe_continue_pwr_meas_read_args; extern apss_complete_args_t G_gpe_complete_pwr_meas_read_args; -extern uint32_t G_pgpe_beacon_address; - extern uint32_t G_proc_fmin_khz; extern uint32_t G_proc_fmax_khz; extern wof_header_data_t G_wof_header; @@ -88,13 +86,8 @@ extern uint8_t G_proc_pmax; IMAGE_HEADER (G_mainAppImageHdr,__ssx_boot,MAIN_APP_ID,ID_NUM_INVALID); -// PGPE Image Header Parameters -uint32_t G_pgpe_shared_sram_address; -uint32_t G_pgpe_shared_sram_sz; -uint32_t G_pgpe_pstate_table_address; -uint32_t G_pgpe_pstate_table_sz; - ppmr_header_t G_ppmr_header; // PPMR Header layout format +pgpe_header_data_t G_pgpe_header; // Selected fields from PGPE Header OCCPstateParmBlock G_oppb; // OCC Pstate Parameters Block Structure extern uint16_t G_proc_fmax_mhz; // max(turbo,uturbo) frequencies @@ -142,7 +135,6 @@ extern uint8_t g_trac_err_buffer[]; void pmc_hw_error_isr(void *private, SsxIrqId irq, int priority); void create_tlb_entry(uint32_t address, uint32_t size); -void read_oppb_params(const OCCPstateParmBlock* occ_ppb); //Macro creates a 'bridge' handler that converts the initial fast-mode to full //mode interrupt handler @@ -388,7 +380,7 @@ END TODO */ OCC_NO_EXTENDED_RC, ERRL_SEV_UNRECOVERABLE, NULL, // tracDesc_t i_trace, - 0, // i_traceSz, + DEFAULT_TRACE_SIZE, //Trace Size l_rc, // i_userData1, 0); // i_userData2 @@ -425,13 +417,14 @@ END TODO */ void create_tlb_entry(uint32_t address, uint32_t size) { +#if PPC405_MMU_SUPPORT int l_rc = SSX_OK; uint32_t tlb_entry_address, tlb_entry_size; // address and size that guarantee page alignment tlb_entry_address = PAGE_ALIGNED_ADDRESS(address); - if(address + (size%PPC405_PAGE_SIZE_MIN) >= - tlb_entry_address + PPC405_PAGE_SIZE_MIN) + if ((address + (size%PPC405_PAGE_SIZE_MIN)) >= + (tlb_entry_address + PPC405_PAGE_SIZE_MIN)) { tlb_entry_size = PAGE_ALIGNED_SIZE(size+PPC405_PAGE_SIZE_MIN); } @@ -440,50 +433,46 @@ void create_tlb_entry(uint32_t address, uint32_t size) tlb_entry_size = PAGE_ALIGNED_SIZE(size); } - -#if PPC405_MMU_SUPPORT // define DTLB for page aligned address and size - l_rc = ppc405_mmu_map( - tlb_entry_address, - tlb_entry_address, - tlb_entry_size, - 0, - TLBLO_I, //Read-only, Cache-inhibited - NULL - ); -#endif - - if(l_rc != SSX_OK) + l_rc = ppc405_mmu_map(tlb_entry_address, + tlb_entry_address, + tlb_entry_size, + 0, + TLBLO_I, //Read-only, Cache-inhibited + NULL); + if(l_rc == SSX_OK) + { + MAIN_TRAC_IMP("Created TLB entry for Address[0x%08x]" + "TLB Page Address[0x%08x], TLB Entry size[0x%08x]", + address, tlb_entry_address, tlb_entry_size); + } + else { MAIN_TRAC_ERR("Failed to create TLB entry," "TLB Page Address[0x%08x], TLB Entry size[0x%08x], rc[0x%08x]", tlb_entry_address, tlb_entry_size, l_rc); - /* @ - * @errortype - * @moduleid CREATE_TLB_ENTRY - * @reasoncode SSX_GENERIC_FAILURE - * @userdata1 ppc405_mmu_map return code - * @userdata2 address for which a TLB entry is created - * @userdata4 ERC_TLB_ENTRY_CREATION_FAILURE - * @devdesc SSX semaphore related failure - */ - - errlHndl_t l_err = createErrl(CREATE_TLB_ENTRY, //modId - SSX_GENERIC_FAILURE, //reasoncode - ERC_TLB_ENTRY_CREATION_FAILURE, //Extended reason code - ERRL_SEV_UNRECOVERABLE, //Severity - NULL, //Trace Buf - DEFAULT_TRACE_SIZE, //Trace Size - l_rc, //userdata1 - address); //userdata2 + /* @ + * @errortype + * @moduleid CREATE_TLB_ENTRY + * @reasoncode SSX_GENERIC_FAILURE + * @userdata1 ppc405_mmu_map return code + * @userdata2 address for which a TLB entry is created + * @userdata4 ERC_TLB_ENTRY_CREATION_FAILURE + * @devdesc SSX semaphore related failure + */ + errlHndl_t l_err = createErrl(CREATE_TLB_ENTRY, //modId + SSX_GENERIC_FAILURE, //reasoncode + ERC_TLB_ENTRY_CREATION_FAILURE, //Extended reason code + ERRL_SEV_UNRECOVERABLE, //Severity + NULL, //Trace Buf + DEFAULT_TRACE_SIZE, //Trace Size + l_rc, //userdata1 + address); //userdata2 - REQUEST_RESET(l_err); + REQUEST_RESET(l_err); } - - MAIN_TRAC_IMP("Created TLB entry for Address[0x%08x]" - "TLB Page Address[0x%08x], TLB Entry size[0x%08x]", - address, tlb_entry_address, tlb_entry_size); +#endif } @@ -493,7 +482,7 @@ void create_tlb_entry(uint32_t address, uint32_t size) * Name: read_wof_header * * Description: Read WOF Tables header and populate global variables - * needed for WOF + * needed for WOF. Must be called after pgpe header is read. * * End Function Specification */ @@ -501,97 +490,156 @@ void read_wof_header(void) { int l_ssxrc = SSX_OK; uint32_t l_reasonCode = 0; - uint32_t l_extReasonCode = 0; - - do - { - // use block copy engine to read WOF header - BceRequest l_wof_header_req; - - // 128 byte aligned buffer to read the data - temp_bce_request_buffer_t l_temp_bce_buff = {{0}}; - - uint32_t pad = g_amec->wof.vfrt_tbls_main_mem_addr%128; - // Force WOF tables address is on 128 byte boundary - uint32_t wof_main_mem_addr_128 = g_amec->wof.vfrt_tbls_main_mem_addr - pad; - // Create request - l_ssxrc = bce_request_create(&l_wof_header_req, // block copy object - &G_pba_bcde_queue, // main to sram copy engine - wof_main_mem_addr_128, // mainstore address - (uint32_t) &l_temp_bce_buff, // SRAM start address - MIN_BCE_REQ_SIZE, // size of copy - SSX_WAIT_FOREVER, // no timeout - NULL, // no call back - NULL, // no call back args - ASYNC_REQUEST_BLOCKING);// blocking request + uint32_t l_extReasonCode = OCC_NO_EXTENDED_RC; + uint32_t userdata1 = 0; + uint32_t userdata2 = 0; - if(l_ssxrc != SSX_OK) - { - CMDH_TRAC_ERR("read_wof_header: BCDE request create failure rc=[%08X]", -l_ssxrc); - /* - * @errortype - * @moduleid READ_WOF_HEADER - * @reasoncode SSX_GENERIC_FAILURE - * @userdata1 RC for BCE block-copy engine - * @userdata2 Internal function checkpoint - * @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE - * @devdesc Failed to create BCDE request - */ - l_reasonCode = SSX_GENERIC_FAILURE; - l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE; - break; - } + MAIN_TRAC_INFO("read_wof_header() 0x%08X", G_pgpe_header.wof_tables_addr); + // Read active quads address, wof tables address, and wof tables len + g_amec->wof.active_quads_sram_addr = G_pgpe_header.requested_active_quad_sram_addr; + g_amec->wof.vfrt_tbls_main_mem_addr = G_pgpe_header.wof_tables_addr; + g_amec->wof.vfrt_tbls_len = G_pgpe_header.wof_tables_length; - // Do the actual copy - l_ssxrc = bce_request_schedule(&l_wof_header_req); + // TODO: RTC 169955 - Read Vratio, Fratio, Vclip, Fclip from shared SRAM + g_amec->wof.v_ratio = 0; + g_amec->wof.f_ratio = 0; + g_amec->wof.v_clip = 0; + g_amec->wof.f_clip = 0; - if(l_ssxrc != SSX_OK) + if (G_pgpe_header.wof_tables_addr != 0) + { + do { - CMDH_TRAC_ERR("read_wof_header: BCE request schedule failure rc=[%08X]", -l_ssxrc); - /* - * @errortype - * @moduleid READ_WOF_HEADER - * @reasoncode SSX_GENERIC_FAILURE - * @userdata1 RC for BCE block-copy engine - * @userdata4 ERC_BCE_REQUEST_SCHEDULE_FAILURE - * @devdesc Failed to read PPMR data by using BCDE - */ - l_reasonCode = SSX_GENERIC_FAILURE; - l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE; - break; - } + // TODO: RTC: 169955 - Updates for new WOF header + // use block copy engine to read WOF header + BceRequest l_wof_header_req; + + // 128 byte aligned buffer to read the data + temp_bce_request_buffer_t l_temp_bce_buff = {{0}}; + + uint32_t pad = G_pgpe_header.wof_tables_addr%128; + // Force WOF tables address is on 128 byte boundary + uint32_t wof_main_mem_addr_128 = G_pgpe_header.wof_tables_addr - pad; + // Create request + l_ssxrc = bce_request_create(&l_wof_header_req, // block copy object + &G_pba_bcde_queue, // main to sram copy engine + wof_main_mem_addr_128, // mainstore address + (uint32_t) &l_temp_bce_buff, // SRAM start address + MIN_BCE_REQ_SIZE, // size of copy + SSX_WAIT_FOREVER, // no timeout + NULL, // no call back + NULL, // no call back args + ASYNC_REQUEST_BLOCKING);// blocking request + if(l_ssxrc != SSX_OK) + { + MAIN_TRAC_ERR("read_wof_header: BCDE request create failure rc=[%08X]", -l_ssxrc); + /* + * @errortype + * @moduleid READ_WOF_HEADER + * @reasoncode SSX_GENERIC_FAILURE + * @userdata1 RC for BCE block-copy engine + * @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE + * @devdesc Failed to create BCDE request + */ + l_reasonCode = SSX_GENERIC_FAILURE; + l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE; + userdata1 = -l_ssxrc; + break; + } - // Copy the data into Global WOF header struct - memcpy(&G_wof_header, &(l_temp_bce_buff.data[pad]), sizeof(wof_header_data_t)); + // Do the actual copy + l_ssxrc = bce_request_schedule(&l_wof_header_req); + if(l_ssxrc != SSX_OK) + { + MAIN_TRAC_ERR("read_wof_header: BCE request schedule failure rc=[%08X]", -l_ssxrc); + /* + * @errortype + * @moduleid READ_WOF_HEADER + * @reasoncode SSX_GENERIC_FAILURE + * @userdata1 RC for BCE block-copy engine + * @userdata4 ERC_BCE_REQUEST_SCHEDULE_FAILURE + * @devdesc Failed to read WOF data using BCDE + */ + l_reasonCode = SSX_GENERIC_FAILURE; + l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE; + userdata1 = -l_ssxrc; + break; + } + // Copy the data into Global WOF header struct + memcpy(&G_wof_header, &(l_temp_bce_buff.data[pad]), sizeof(wof_header_data_t)); - // Make sure the header is reporting a valid number of quads i.e. 1 or 6 - if( (G_wof_header.active_quads_size != ACTIVE_QUAD_SZ_MIN) && - (G_wof_header.active_quads_size != ACTIVE_QUAD_SZ_MAX) ) - { - CMDH_TRAC_ERR("read_wof_header: Invalid number of active quads!" - " Expected: 1 or 6, Actual %d", - G_wof_header.active_quads_size ); + // verify the validity of the magic number + uint32_t magic_number = in32(G_pgpe_header.wof_tables_addr); + MAIN_TRAC_INFO("read_wof_header() Magic No: 0x%08X", magic_number); + if(WOF_MAGIC_NUMBER == magic_number) + { + // Make sure the header is reporting a valid number of quads i.e. 1 or 6 + if( (G_wof_header.active_quads_size != ACTIVE_QUAD_SZ_MIN) && + (G_wof_header.active_quads_size != ACTIVE_QUAD_SZ_MAX) ) + { + MAIN_TRAC_ERR("read_wof_header: Invalid number of active quads!" + " Expected: 1 or 6, Actual %d, WOF disabled", + G_wof_header.active_quads_size ); + /* + * @errortype + * @moduleid READ_WOF_HEADER + * @reasoncode INVALID_ACTIVE_QUAD_COUNT + * @userdata1 Reported active quad count + * @userdata4 ERC_WOF_QUAD_COUNT_FAILURE + * @devdesc Read an invalid number of active quads + */ + l_reasonCode = INVALID_ACTIVE_QUAD_COUNT; + l_extReasonCode = ERC_WOF_QUAD_COUNT_FAILURE; + userdata1 = G_wof_header.active_quads_size; + break; + } + } + else + { + MAIN_TRAC_ERR("read_wof_header: Invalid WOF Magic number. Address[0x%08X], Magic Number[0x%08X], WOF disabled", + G_pgpe_header.wof_tables_addr, magic_number); + /* @ + * @errortype + * @moduleid READ_WOF_HEADER + * @reasoncode INVALID_MAGIC_NUMBER + * @userdata1 WOF header sram address + * @userdata2 read WOF magic number + * @userdata4 OCC_NO_EXTENDED_RC + * @devdesc Invalid WOF magic number, WOF disabled + */ + l_reasonCode = INVALID_MAGIC_NUMBER; + userdata1 = G_pgpe_header.wof_tables_addr; + userdata2 = magic_number; + break; + } - /* - * @errortype - * @moduleid READ_WOF_HEADER - * @reasoncode INVALID_ACTIVE_QUAD_COUNT - * @userdata1 Reported active quad count - * @userdata4 Quad count failure - * @devdesc Read an invalid number of active quads - */ - l_reasonCode = INVALID_ACTIVE_QUAD_COUNT; - l_extReasonCode = ERC_WOF_QUAD_COUNT_FAILURE; - errlHndl_t l_errl = createErrl(READ_WOF_HEADER, //modId - INVALID_ACTIVE_QUAD_COUNT, //reasoncode - ERC_WOF_QUAD_COUNT_FAILURE, //Extended reason code - ERRL_SEV_UNRECOVERABLE, //Severity - NULL, //Trace Buf - 0, //Trace Size - G_wof_header.active_quads_size, //userdata1 - 0); //userdata2 + // Make wof header data visible to amester + g_amec->wof.size_of_vfrt = G_wof_header.size_of_vfrt; + g_amec->wof.vfrt_data_size = G_wof_header.vfrt_data_size; + g_amec->wof.active_quads_start = G_wof_header.active_quads_start; + g_amec->wof.active_quads_size = G_wof_header.active_quads_size; + g_amec->wof.vdn_start = G_wof_header.vdn_start; + g_amec->wof.vdn_step = G_wof_header.vdn_step; + g_amec->wof.vdn_size = G_wof_header.vdn_size; + g_amec->wof.vdd_start = G_wof_header.vdd_start; + g_amec->wof.vdd_step = G_wof_header.vdd_step; + g_amec->wof.vdd_size = G_wof_header.vdd_size; + + }while( 0 ); + + // Check for errors and log, if any + if (l_reasonCode) + { + errlHndl_t l_errl = createErrl(READ_WOF_HEADER, //modId + l_reasonCode, //reasoncode + l_extReasonCode, //Extended reason code + ERRL_SEV_UNRECOVERABLE, //Severity + NULL, //Trace Buf + DEFAULT_TRACE_SIZE, //Trace Size + userdata1, //userdata1 + userdata2); //userdata2 // Callout firmware addCalloutToErrl(l_errl, @@ -602,54 +650,17 @@ void read_wof_header(void) // Commit error log commitErrl(&l_errl); - // We were unable to get the active quad count. Do not run wof algo. - g_amec->wof.wof_disabled |= WOF_RC_INVALID_ACTIVE_QUADS_MASK; - - break; + // We were unable to get the WOF header thus it should not be run. + g_amec->wof.wof_disabled |= WOF_RC_NO_WOF_HEADER_MASK; } - - // Make wof header data visible to amester - g_amec->wof.size_of_vfrt = G_wof_header.size_of_vfrt; - g_amec->wof.vfrt_data_size = G_wof_header.vfrt_data_size; - g_amec->wof.active_quads_start = G_wof_header.active_quads_start; - g_amec->wof.active_quads_size = G_wof_header.active_quads_size; - g_amec->wof.vdn_start = G_wof_header.vdn_start; - g_amec->wof.vdn_step = G_wof_header.vdn_step; - g_amec->wof.vdn_size = G_wof_header.vdn_size; - g_amec->wof.vdd_start = G_wof_header.vdd_start; - g_amec->wof.vdd_step = G_wof_header.vdd_step; - g_amec->wof.vdd_size = G_wof_header.vdd_size; - - }while( 0 ); - - // Check for errors and log, if any - if( l_ssxrc != SSX_OK ) + } + else { - errlHndl_t l_errl = createErrl(READ_WOF_HEADER, //modId - l_reasonCode, //reasoncode - l_extReasonCode, //Extended reason code - ERRL_SEV_UNRECOVERABLE, //Severity - NULL, //Trace Buf - 0, //Trace Size - -l_ssxrc, //userdata1 - 0); //userdata2 - - // Callout firmware - addCalloutToErrl(l_errl, - ERRL_CALLOUT_TYPE_COMPONENT_ID, - ERRL_COMPONENT_ID_FIRMWARE, - ERRL_CALLOUT_PRIORITY_HIGH); - - // Commit error log - commitErrl(&l_errl); - // We were unable to get the WOF header thus it should not be run. + MAIN_TRAC_INFO("read_wof_header(): WOF header address is 0, WOF is disabled"); g_amec->wof.wof_disabled |= WOF_RC_NO_WOF_HEADER_MASK; - return; - } -} - +} // end read_wof_header() /* @@ -662,99 +673,108 @@ void read_wof_header(void) * Initialize OCC/PGPE shared SRAM entry in the DTLB, * Populate global variables, including G_pgpe_peacon_address. * + * Returns: TRUE if read was successful, else FALSE + * * End Function Specification */ -void read_pgpe_header(void) +bool read_pgpe_header(void) { - uint64_t magic_number; - errlHndl_t l_err; - - // define DTLB for the PGPE image header - create_tlb_entry(PGPE_HEADER_ADDR, PGPE_HEADER_SZ); + uint32_t l_reasonCode = 0; + uint32_t l_extReasonCode = OCC_NO_EXTENDED_RC; + uint32_t userdata1 = 0; + uint32_t userdata2 = 0; + uint64_t magic_number = 0; - // verify the validity of the magic number - magic_number = in64(PGPE_HEADER_ADDR); - if(PGPE_MAGIC_NUMBER != magic_number) + MAIN_TRAC_INFO("read_pgpe_header(0x%08X)", PGPE_HEADER_ADDR); + do { - // The Magic number is invalid .. Invalid or corrupt PGPE image header - MAIN_TRAC_ERR("Invalid PGPGE Magic number. Address[0x%08X], Magic Number[0x%08X%08X]", - PGPE_HEADER_ADDR, (uint32_t)(magic_number>>32), (uint32_t)magic_number); - /* @ - * @errortype - * @moduleid READ_PGPE_HEADER - * @reasoncode INVALID_MAGIC_NUMBER - * @userdata1 Low order 32 bits of retrieved PGPE magic number - * @userdata2 Hight order 32 bits of retrieved PGPE magic number - * @userdata4 OCC_NO_EXTENDED_RC - * @devdesc SSX semaphore related failure - */ - - l_err = createErrl(READ_PGPE_HEADER, //modId - INVALID_MAGIC_NUMBER, //reasoncode - OCC_NO_EXTENDED_RC, //Extended reason code - ERRL_SEV_UNRECOVERABLE, //Severity - NULL, //Trace Buf - DEFAULT_TRACE_SIZE, //Trace Size - (uint32_t)magic_number, //userdata1 - (uint32_t)(magic_number>>32)); //userdata2 - - REQUEST_RESET(l_err); - - } + // verify the validity of the magic number + magic_number = in64(PGPE_HEADER_ADDR); + if (PGPE_MAGIC_NUMBER_10 == magic_number) + { + G_pgpe_header.shared_sram_addr = in32(PGPE_HEADER_ADDR + PGPE_SHARED_SRAM_ADDR_OFFSET); + G_pgpe_header.shared_sram_length = in32(PGPE_HEADER_ADDR + PGPE_SHARED_SRAM_LEN_OFFSET); + G_pgpe_header.occ_pstate_table_sram_addr = in32(PGPE_HEADER_ADDR + PGPE_OCC_PSTATE_TBL_ADDR_OFFSET); + G_pgpe_header.occ_pstate_table_length = in32(PGPE_HEADER_ADDR + PGPE_OCC_PSTATE_TBL_SZ_OFFSET); + G_pgpe_header.beacon_sram_addr = in32(PGPE_HEADER_ADDR + PGPE_BEACON_ADDR_OFFSET); + G_pgpe_header.actual_quad_status_sram_addr = in32(PGPE_HEADER_ADDR + PGPE_ACTUAL_QUAD_STATUS_ADDR_OFFSET); + G_pgpe_header.wof_state_address = in32(PGPE_HEADER_ADDR + PGPE_WOF_STATE_ADDR_OFFSET); + G_pgpe_header.requested_active_quad_sram_addr = in32(PGPE_HEADER_ADDR + PGPE_REQUESTED_ACTIVE_QUAD_ADDR_OFFSET); + G_pgpe_header.wof_tables_addr = in32(PGPE_HEADER_ADDR + PGPE_WOF_TBLS_ADDR_OFFSET); + G_pgpe_header.wof_tables_length = in32(PGPE_HEADER_ADDR + PGPE_WOF_TBLS_LEN_OFFSET); + + MAIN_TRAC_IMP("Shared SRAM Address[0x%08x], PGPE Beacon Address[0x%08x]", + G_pgpe_header.shared_sram_addr, G_pgpe_header.beacon_sram_addr); + MAIN_TRAC_IMP("WOF Tables Main Memory Address[0x%08x], Len[0x%08x], " + "Req Active Quads Address[0x%08x]", + G_pgpe_header.wof_tables_addr, + G_pgpe_header.wof_tables_length, + G_pgpe_header.requested_active_quad_sram_addr); + if ((G_pgpe_header.beacon_sram_addr == 0) || + (G_pgpe_header.shared_sram_addr == 0)) + { + /* + * @errortype + * @moduleid READ_PGPE_HEADER + * @reasoncode SSX_GENERIC_FAILURE + * @userdata1 lower word of beacon sram address + * @userdata2 lower word of shared sram address + * @userdata4 ERC_PGPE_INVALID_ADDRESS + * @devdesc Invalid sram addresses from PGPE header + */ + l_reasonCode = SSX_GENERIC_FAILURE; + l_extReasonCode = ERC_PGPE_INVALID_ADDRESS; + userdata1 = WORD_LOW(G_pgpe_header.beacon_sram_addr); + userdata2 = WORD_LOW(G_pgpe_header.shared_sram_addr); + break; + } + } + else + { + // The Magic number is invalid .. Invalid or corrupt PGPE image header + MAIN_TRAC_ERR("read_pgpe_header: Invalid PGPE Magic number. Address[0x%08X], Magic Number[0x%08X%08X]", + PGPE_HEADER_ADDR, WORD_HIGH(magic_number), WORD_LOW(magic_number)); + /* @ + * @errortype + * @moduleid READ_PGPE_HEADER + * @reasoncode INVALID_MAGIC_NUMBER + * @userdata1 High order 32 bits of retrieved PGPE magic number + * @userdata2 Low order 32 bits of retrieved PGPE magic number + * @userdata4 OCC_NO_EXTENDED_RC + * @devdesc Invalid magic number in PGPE header + */ + l_reasonCode = INVALID_MAGIC_NUMBER; + userdata1 = WORD_HIGH(magic_number); + userdata2 = WORD_LOW(magic_number); + break; + } + } while (0); - if(l_err == NULL) + if ( l_reasonCode ) { - // Read PGPE Beacon address from PGPE image header - G_pgpe_beacon_address = in32(PGPE_BEACON_ADDR_PTR); - - MAIN_TRAC_IMP("Read PGPE Beacon Address[0x%08x]", - G_pgpe_beacon_address); - - // Read active quads address, wof tables address, and wof tables len - g_amec->wof.active_quads_sram_addr = in32(PGPE_ACTIVE_QUAD_ADDR_PTR); - g_amec->wof.vfrt_tbls_main_mem_addr = in32(PGPE_WOF_TBLS_ADDR_PTR); - g_amec->wof.vfrt_tbls_len = in32(PGPE_WOF_TBLS_LEN_PTR); - - - MAIN_TRAC_IMP("Read WOF Tables Main Memory Address[0x%08x], Len[0x%08x]," - " Active Quads Address[0x%08x]", - g_amec->wof.vfrt_tbls_main_mem_addr, - g_amec->wof.vfrt_tbls_len, - g_amec->wof.active_quads_sram_addr ); - - // TODO: RTC 169955 - Read Vratio, Fratio, Vclip, Fclip from shared SRAM - g_amec->wof.v_ratio = 0; - g_amec->wof.f_ratio = 0; - g_amec->wof.v_clip = 0; - g_amec->wof.f_clip = 0; - // Extract important WOF data into global space - read_wof_header(); - - // Read OCC/PGPE Shared SRAM address and size - G_pgpe_shared_sram_address = in32(PGPE_SHARED_SRAM_ADDR_PTR); - G_pgpe_shared_sram_sz = in32(PGPE_SHARED_SRAM_SZ_PTR); + errlHndl_t l_errl = createErrl(READ_PGPE_HEADER, //modId + l_reasonCode, //reasoncode + l_extReasonCode, //Extended reason code + ERRL_SEV_UNRECOVERABLE, //Severity + NULL, //Trace Buf + DEFAULT_TRACE_SIZE, //Trace Size + userdata1, //userdata1 + userdata2); //userdata2 - MAIN_TRAC_IMP("Read PGPE Shared SRAM Start Address[0x%08x], Size[0x%08x]", - G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz); + // Callout firmware + addCalloutToErrl(l_errl, + ERRL_CALLOUT_TYPE_COMPONENT_ID, + ERRL_COMPONENT_ID_FIRMWARE, + ERRL_CALLOUT_PRIORITY_HIGH); - // Read OCC Pstate table address and size - G_pgpe_pstate_table_address = in32(PGPE_PSTATE_TBL_ADDR_PTR); - G_pgpe_pstate_table_sz = in32(PGPE_PSTATE_TBL_SZ_PTR); + REQUEST_RESET(l_errl); + return FALSE; + } + // Success + return TRUE; - // PGPE Beacon is not implemented in simics yet - // the G_pgpe_shared_sram_address and G_pgpe_shared_sram_sz pointers don't - // have the proper values yet. - // @TODO: remove this condition when PGPE code is integrated. RTC: 163934 - if(!G_simics_environment) - { - // define DTLB for OCC/PGPE shared SRAM, which enables access - // to OCC-PGPE Shared SRAM space, including pgpe_beacon - create_tlb_entry(G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz); - } - } - return; -} +} // end read_pgpe_header() /* @@ -762,21 +782,21 @@ void read_pgpe_header(void) * * Name: read_ppmr_header * - * Description: read PPMR image header, and extract the - * OPPB HOMER offset and sturcture size.. + * Description: read PPMR image header and validate magic number + * + * Returns: TRUE if read was successful, else FALSE * * End Function Specification */ -void read_ppmr_header(void) +bool read_ppmr_header(void) { int l_ssxrc = SSX_OK; uint32_t l_reasonCode = 0; - uint32_t l_extReasonCode = 0; - - // error log parameters, if any + uint32_t l_extReasonCode = OCC_NO_EXTENDED_RC; uint32_t userdata1 = 0; uint32_t userdata2 = 0; + MAIN_TRAC_INFO("read_ppmr_header(0x%08X)", PPMR_ADDRESS_HOMER); // create a DTLB entry for the PPMR image header create_tlb_entry(PPMR_ADDRESS_HOMER, sizeof(ppmr_header_t)); @@ -835,31 +855,25 @@ void read_ppmr_header(void) break; } - if(G_ppmr_header.oppb_length != sizeof(OCCPstateParmBlock)) + if (PPMR_MAGIC_NUMBER_10 != G_ppmr_header.magic_number) { - MAIN_TRAC_ERR("read_ppmr_header: OCCPstateParmBlock size mismatch:" - "PPMR header sz[0x%08x] PPMR struct sz[0x%08x]", - G_ppmr_header.oppb_length, sizeof(OCCPstateParmBlock)); - - /* + MAIN_TRAC_ERR("read_ppmr_header: Invalid PPMR Magic number: 0x%08X%08X", + WORD_HIGH(G_ppmr_header.magic_number), WORD_LOW(G_ppmr_header.magic_number)); + /* @ * @errortype * @moduleid READ_PPMR_HEADER - * @reasoncode PGPE_FAILURE - * @userdata1 G_ppmr_header.oppb_length - * @userdata2 sizeof(OCCPstateParmBlock) - * @userdata4 ERC_PGPE_PPMR_OPPB_SIZE_MISMATCH - * @devdesc PPMR's OPPB size mismatches data structure's + * @reasoncode INVALID_MAGIC_NUMBER + * @userdata1 High order 32 bits of retrieved PPMR magic number + * @userdata2 Low order 32 bits of retrieved PPMR magic number + * @userdata4 OCC_NO_EXTENDED_RC + * @devdesc Invalid magic number in PPMR header */ - l_reasonCode = SSX_GENERIC_FAILURE; - l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE; - - userdata1 = G_ppmr_header.oppb_length; - userdata2 = sizeof(OCCPstateParmBlock); + l_reasonCode = INVALID_MAGIC_NUMBER; + userdata1 = WORD_HIGH(G_ppmr_header.magic_number); + userdata2 = WORD_LOW(G_ppmr_header.magic_number); break; } - - } while (0); if ( l_reasonCode ) @@ -869,7 +883,7 @@ void read_ppmr_header(void) l_extReasonCode, //Extended reason code ERRL_SEV_UNRECOVERABLE, //Severity NULL, //Trace Buf - 0, //Trace Size + DEFAULT_TRACE_SIZE, //Trace Size userdata1, //userdata1 userdata2); //userdata2 @@ -881,11 +895,11 @@ void read_ppmr_header(void) REQUEST_RESET(l_errl); - return; + return FALSE; } - // Read OCC pstates parameter block - read_oppb_params((OCCPstateParmBlock*)G_ppmr_header.oppb_offset); + // Success + return TRUE; } /* @@ -896,19 +910,24 @@ void read_ppmr_header(void) * Description: Read the OCC Pstates Parameter Block, * and initializa Pstates Global Variables. * + * Returns: TRUE if read was successful, else FALSE + * * End Function Specification */ -void read_oppb_params(const OCCPstateParmBlock* oppb_offset) +bool read_oppb_params(const OCCPstateParmBlock* oppb_offset) { int l_ssxrc = SSX_OK; uint32_t l_reasonCode = 0; - uint32_t l_extReasonCode = 0; + uint32_t l_extReasonCode = OCC_NO_EXTENDED_RC; + uint32_t userdata1 = 0; + uint32_t userdata2 = 0; - create_tlb_entry( ((uint32_t)oppb_offset + (uint32_t)PPMR_ADDRESS_HOMER), - sizeof(OCCPstateParmBlock)); + MAIN_TRAC_INFO("read_oppb_params(0x%08X)", PPMR_ADDRESS_HOMER + oppb_offset); + create_tlb_entry(((uint32_t)PPMR_ADDRESS_HOMER + (uint32_t)oppb_offset), + sizeof(OCCPstateParmBlock)); do{ - // use block copy engine to read the PPMR header + // use block copy engine to read the OPPB header BceRequest pba_copy; // Set up a copy request @@ -925,18 +944,18 @@ void read_oppb_params(const OCCPstateParmBlock* oppb_offset) if(l_ssxrc != SSX_OK) { - CMDH_TRAC_ERR("read_oppb_params: BCDE request create failure rc=[%08X]", -l_ssxrc); + MAIN_TRAC_ERR("read_oppb_params: BCDE request create failure rc=[%08X]", -l_ssxrc); /* * @errortype * @moduleid READ_OPPB_PARAMS * @reasoncode SSX_GENERIC_FAILURE * @userdata1 RC for BCE block-copy engine - * @userdata2 Internal function checkpoint * @userdata4 ERC_BCE_REQUEST_CREATE_FAILURE * @devdesc Failed to create BCDE request */ l_reasonCode = SSX_GENERIC_FAILURE; l_extReasonCode = ERC_BCE_REQUEST_CREATE_FAILURE; + userdata1 = (uint32_t)(-l_ssxrc); break; } @@ -945,36 +964,78 @@ void read_oppb_params(const OCCPstateParmBlock* oppb_offset) if(l_ssxrc != SSX_OK) { - CMDH_TRAC_ERR("read_oppb_params: BCE request schedule failure rc=[%08X]", -l_ssxrc); + MAIN_TRAC_ERR("read_oppb_params: BCE request schedule failure rc=[%08X]", -l_ssxrc); /* * @errortype * @moduleid READ_OPPB_PARAMS * @reasoncode SSX_GENERIC_FAILURE * @userdata1 RC for BCE block-copy engine * @userdata4 ERC_BCE_REQUEST_SCHEDULE_FAILURE - * @devdesc Failed to read PPMR data by using BCDE + * @devdesc Failed to read OPPB data by using BCDE */ l_reasonCode = SSX_GENERIC_FAILURE; l_extReasonCode = ERC_BCE_REQUEST_SCHEDULE_FAILURE; + userdata1 = (uint32_t)(-l_ssxrc); + break; + } + + if (OPPB_MAGIC_NUMBER_10 != G_oppb.magic) + { + // The magic number is invalid .. Invalid or corrupt OPPB image header + MAIN_TRAC_ERR("read_oppb_header: Invalid OPPB magic number: 0x%08X%08X", + WORD_HIGH(G_oppb.magic), WORD_LOW(G_oppb.magic)); + /* @ + * @errortype + * @moduleid READ_OPPB_PARAMS + * @reasoncode INVALID_MAGIC_NUMBER + * @userdata1 High order 32 bits of retrieved OPPB magic number + * @userdata2 Low order 32 bits of retrieved OPPB magic number + * @userdata4 OCC_NO_EXTENDED_RC + * @devdesc Invalid magic number in OPPB header + */ + l_reasonCode = INVALID_MAGIC_NUMBER; + userdata1 = WORD_HIGH(G_oppb.magic); + userdata2 = WORD_LOW(G_oppb.magic); break; } - } while (0); - // Read WOF addresses + // Validate frequencies + // frequency_min_khz frequency_max_khz frequency_step_khz pstate_min + if ((G_oppb.frequency_min_khz == 0) || (G_oppb.frequency_max_khz == 0) || + (G_oppb.frequency_step_khz == 0) || (G_oppb.pstate_min == 0) || + (G_oppb.frequency_min_khz > G_oppb.frequency_max_khz)) + { + // The magic number is invalid .. Invalid or corrupt OPPB image header + MAIN_TRAC_ERR("read_oppb_header: Invalid frequency data: min[%d], max[%d], step[%d], pmin[%d] kHz", + G_oppb.frequency_min_khz, G_oppb.frequency_max_khz, + G_oppb.frequency_step_khz, G_oppb.pstate_min); + /* @ + * @errortype + * @moduleid READ_OPPB_PARAMS + * @reasoncode INVALID_FREQUENCY + * @userdata1 min / max frequency (MHz) + * @userdata2 step freq (MHz) / pstate min + * @userdata4 OCC_NO_EXTENDED_RC + * @devdesc Invalid frequency in OPPB header + */ + l_reasonCode = INVALID_FREQUENCY; + userdata1 = ((G_oppb.frequency_min_khz/1000) << 16) | (G_oppb.frequency_max_khz/1000); + userdata2 = ((G_oppb.frequency_step_khz/1000) << 16) | G_oppb.pstate_min; + break; + } - MAIN_TRAC_IMP("Read PGPE Shared SRAM Start Address[0x%08x], Size[0x%08x]", - G_pgpe_shared_sram_address, G_pgpe_shared_sram_sz); + } while (0); - if ( l_ssxrc != SSX_OK ) + if (l_reasonCode) { errlHndl_t l_errl = createErrl(READ_OPPB_PARAMS, //modId l_reasonCode, //reasoncode l_extReasonCode, //Extended reason code ERRL_SEV_UNRECOVERABLE, //Severity NULL, //Trace Buf - 0, //Trace Size - -l_ssxrc, //userdata1 - 0); //userdata2 + DEFAULT_TRACE_SIZE, //Trace Size + userdata1, //userdata1 + userdata2); //userdata2 // Callout firmware addCalloutToErrl(l_errl, @@ -984,7 +1045,7 @@ void read_oppb_params(const OCCPstateParmBlock* oppb_offset) REQUEST_RESET(l_errl); - return; + return FALSE; } // Copy over max frequency into G_proc_fmax_mhz @@ -998,6 +1059,50 @@ void read_oppb_params(const OCCPstateParmBlock* oppb_offset) G_mhz_per_pstate = G_oppb.frequency_step_khz/1000; TRAC_INFO("read_oppb_params: OCC Pstates Parameter Block read successfully"); + + // Success + return TRUE; +} + + +/* + * Function Specification + * + * Name: read_hcode_headers + * + * Description: Read and save hcode header data + * + * End Function Specification + */ +void read_hcode_headers() +{ + do + { + CHECKPOINT(READ_HCODE_HEADERS); + + if (read_ppmr_header() == FALSE) break; + CHECKPOINT(PPMR_IMAGE_HEADER_READ); + + // Read OCC pstates parameter block + if (read_oppb_params((OCCPstateParmBlock*)G_ppmr_header.oppb_offset) == FALSE) break; + CHECKPOINT(OPPB_IMAGE_HEADER_READ); + + // Read PGPE header file, extract OCC/PGPE Shared SRAM address and size, + if (read_pgpe_header() == FALSE) break; + CHECKPOINT(PGPE_IMAGE_HEADER_READ); + + // Extract important WOF data into global space + read_wof_header(); + CHECKPOINT(WOF_IMAGE_HEADER_READ); + + // PGPE Beacon is not implemented in simics yet + if(!G_simics_environment) + { + // define DTLB for OCC/PGPE shared SRAM, which enables access + // to OCC-PGPE Shared SRAM space, including pgpe_beacon + create_tlb_entry(G_pgpe_header.shared_sram_addr, G_pgpe_header.shared_sram_length); + } + } while(0); } /* @@ -1105,7 +1210,7 @@ void occ_ipc_setup() OCC_NO_EXTENDED_RC, ERRL_SEV_UNRECOVERABLE, NULL, // tracDesc_t i_trace, - 0, // i_traceSz, + DEFAULT_TRACE_SIZE, //Trace Size l_rc, // i_userData1, 0); // i_userData2 @@ -1504,15 +1609,8 @@ void Main_thread_routine(void *private) TRAC_INFO("Main_thread_routine: Pstate Key globals initialized to default values"); #else - // Read PGPE header file, extract OCC/PGPE Shared SRAM address and size, - // Read other global parameters, e.g. G_pgpe_beacon_address, etc. - read_pgpe_header(); - CHECKPOINT(PGPE_IMAGE_HEADER_READ); - - // Read PPMR header, extract OCC pstates parameter block address and size, - // Read OCCC pstate parameter block. - read_ppmr_header(); - CHECKPOINT(PPMR_IMAGE_HEADER_READ); + // Read hcode headers (PPMR, OCC pstate parameter block, PGPE, WOF) + read_hcode_headers(); #endif // Initialize watchdog timers. This needs to be right before diff --git a/src/occ_405/occ_service_codes.h b/src/occ_405/occ_service_codes.h index 83b1ed0..1ab791b 100644 --- a/src/occ_405/occ_service_codes.h +++ b/src/occ_405/occ_service_codes.h @@ -122,9 +122,8 @@ enum occReasonCode WOF_VFRT_REQ_FAILURE = 0xD8, INVALID_MAGIC_NUMBER = 0xDA, - DIVIDE_BY_ZERO_ERROR = 0xDB, - + INVALID_FREQUENCY = 0xDC, /// Success! OCC_SUCCESS_REASON_CODE = 0xFF, @@ -243,6 +242,7 @@ enum occExtReasonCode ERC_PGPE_PPMR_OPPB_SIZE_MISMATCH = 0x00B8, ERC_PGPE_ACTIVE_TO_OBSERVATION_TIMEOUT = 0x00B9, ERC_PGPE_TASK_TIMEOUT = 0x00BA, + ERC_PGPE_INVALID_ADDRESS = 0x00BB, ERC_WOF_QUAD_COUNT_FAILURE = 0x00C0, diff --git a/src/occ_405/pgpe/pgpe_shared.h b/src/occ_405/pgpe/pgpe_shared.h index e74d843..30acd5b 100644 --- a/src/occ_405/pgpe/pgpe_shared.h +++ b/src/occ_405/pgpe/pgpe_shared.h @@ -24,44 +24,22 @@ /* IBM_PROLOG_END_TAG */ #define PGPE_HEADER_ADDR 0xFFF20180 // 0xfff20000 + 0x180 -#define PGPE_HEADER_SZ 96 // Size of PGPE Image header -#define PGPE_MAGIC_NUMBER 0x5849502050475045ull // "XIP PGPE" +#define PPMR_MAGIC_NUMBER_10 0x50504D525F312E30ull // "PPMR_1.0" +#define OPPB_MAGIC_NUMBER_10 0x4F43435050423030ull // "OCCPPB00" +#define PGPE_MAGIC_NUMBER_10 0x504750455F312E30ull // "PGPE_1.0" // Offset addresses of PGPE Header parameters (relative to start address) -#define PGPE_SHARED_SRAM_ADDR_OFFSET 0x0c -#define PGPE_SHARED_SRAM_SZ_OFFSET 0x14 -#define PGPE_PSTATE_TBL_ADDR_OFFSET 0x40 -#define PGPE_PSTATE_TBL_SZ_OFFSET 0x44 -#define PGPE_BEACON_ADDR_OFFSET 0x48 -#define PGPE_ACTIVE_QUAD_ADDR_OFFSET 0x4c -#define PGPE_WOF_TBLS_ADDR_OFFSET 0x50 -#define PGPE_WOF_TBLS_LEN_OFFSET 0x54 - -// Offset addresses of OCC-PGPE Shared SRAM pointers (relative to Shared SRAM ptr) - -// PGPE Image Header Parameter addresses - -//Shared OCC-PGPE SRAM parameters -#define PGPE_SHARED_SRAM_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_SHARED_SRAM_ADDR_OFFSET) -#define PGPE_SHARED_SRAM_SZ_PTR (PGPE_HEADER_ADDR + PGPE_SHARED_SRAM_SZ_OFFSET) - - -// A pointer to PGPE Beacon Address -#define PGPE_BEACON_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_BEACON_ADDR_OFFSET) - -// Pointers to data needed by WOF -#define PGPE_ACTIVE_QUAD_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_ACTIVE_QUAD_ADDR_OFFSET) -#define PGPE_WOF_TBLS_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_ADDR_OFFSET) -#define PGPE_WOF_TBLS_LEN_PTR (PGPE_HEADER_ADDR + PGPE_WOF_TBLS_LEN_OFFSET) - -// Pointers to Pstate tables in SRAM -#define PGPE_PSTATE_TBL_ADDR_PTR (PGPE_HEADER_ADDR + PGPE_PSTATE_TBL_ADDR_OFFSET) -#define PGPE_PSTATE_TBL_SZ_PTR (PGPE_HEADER_ADDR + PGPE_PSTATE_TBL_SZ_OFFSET) - -// PPMR (Pstates PM region) in HOMMR -#define PPMR_OPPM_ADDR_OFFSET 0x40 //offset of the OCC Pstates Parameter Block address in the PPMR header -#define PPMR_OPPM_SZ_OFFSET 0x44 //offset of the OCC Pstates Parameter Block size in the PPMR header +#define PGPE_SHARED_SRAM_ADDR_OFFSET 0x0c +#define PGPE_SHARED_SRAM_LEN_OFFSET 0x14 +#define PGPE_OCC_PSTATE_TBL_ADDR_OFFSET 0x40 +#define PGPE_OCC_PSTATE_TBL_SZ_OFFSET 0x44 +#define PGPE_BEACON_ADDR_OFFSET 0x48 +#define PGPE_ACTUAL_QUAD_STATUS_ADDR_OFFSET 0x4c +#define PGPE_WOF_STATE_ADDR_OFFSET 0x50 +#define PGPE_REQUESTED_ACTIVE_QUAD_ADDR_OFFSET 0x54 +#define PGPE_WOF_TBLS_ADDR_OFFSET 0x58 +#define PGPE_WOF_TBLS_LEN_OFFSET 0x5C // This size must be a multiple of 128 @@ -69,10 +47,10 @@ typedef struct __attribute__ ((packed)) { uint64_t magic_number; uint32_t bc_offset; - uint32_t resserved; + uint32_t reserved; uint32_t bl_offset; uint32_t bl_length; - uint32_t build_date;; + uint32_t build_date; uint32_t version; uint8_t resvd_flag[8]; uint32_t pgpe_hcode_offset; @@ -87,3 +65,23 @@ typedef struct __attribute__ ((packed)) uint32_t pstables_length; uint8_t pad[48]; } ppmr_header_t __attribute__ ((aligned (128))); + + +typedef struct __attribute__ ((packed)) +{ + uint32_t shared_sram_addr; + uint32_t shared_sram_length; + uint32_t occ_pstate_table_sram_addr; + uint32_t occ_pstate_table_length; + uint32_t beacon_sram_addr; + uint32_t actual_quad_status_sram_addr; + uint32_t wof_state_address; + uint32_t requested_active_quad_sram_addr; + uint32_t wof_tables_addr; + uint32_t wof_tables_length; +} pgpe_header_data_t; + +extern pgpe_header_data_t G_pgpe_header; + + + diff --git a/src/occ_405/ssx_app_cfg.h b/src/occ_405/ssx_app_cfg.h index cf9c47a..1418d0b 100755 --- a/src/occ_405/ssx_app_cfg.h +++ b/src/occ_405/ssx_app_cfg.h @@ -72,7 +72,12 @@ do { \ /// IRQ#, TYPE, POLARITY, ENABLE /// #define APPCFG_EXT_IRQS_CONFIG \ + OCCHW_IRQ_GPE0_HALT OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ + OCCHW_IRQ_GPE1_HALT OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ + OCCHW_IRQ_PPC405_HALT OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_CHECK_STOP_PPC405 OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ + OCCHW_IRQ_OCB_ERROR OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ + OCCHW_IRQ_SPIPSS_ERROR OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_EXTERNAL_TRAP OCCHW_IRQ_TYPE_LEVEL OCCHW_IRQ_POLARITY_HI OCCHW_IRQ_MASKED \ OCCHW_IRQ_OCC_TIMER0 OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_OCC_TIMER1 OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ diff --git a/src/occ_405/state.c b/src/occ_405/state.c index c7d931e..36c1ec3 100755 --- a/src/occ_405/state.c +++ b/src/occ_405/state.c @@ -133,12 +133,12 @@ inline bool SMGR_is_state_transitioning(void) errlHndl_t SMGR_standby_to_observation() { errlHndl_t l_errlHndl = NULL; - static bool l_error_logged = FALSE; // To prevent trace and error log happened over and over + static bool L_error_logged = FALSE; // To prevent trace and error log happened over and over if( SMGR_MASK_OBSERVATION_READY == (SMGR_validate_get_valid_states() & SMGR_MASK_OBSERVATION_READY)) { - l_error_logged = FALSE; + L_error_logged = FALSE; TRAC_IMP("SMGR: Standby to Observation Transition Started"); memory_init(); @@ -154,10 +154,10 @@ errlHndl_t SMGR_standby_to_observation() TRAC_IMP("SMGR: Standby to Observation Transition Completed"); } - else if(FALSE == l_error_logged) + else if(FALSE == L_error_logged) { - l_error_logged = TRUE; - TRAC_ERR("SMGR: Standby to Observation Transition Failed"); + L_error_logged = TRUE; + TRAC_ERR("SMGR: Standby to Observation Transition Failed due to not OBS_READY"); /* @ * @errortype * @moduleid MAIN_STATE_TRANSITION_MID @@ -196,7 +196,7 @@ errlHndl_t SMGR_standby_to_characterization() { errlHndl_t l_errlHndl = NULL; int rc = 0; - static bool l_error_logged = FALSE; // To prevent trace and error log happened over and over + static bool L_error_logged = FALSE; // To prevent trace and error log happened over and over Pstate l_pstate; do { @@ -204,7 +204,7 @@ errlHndl_t SMGR_standby_to_characterization() if( SMGR_MASK_ACTIVE_READY == (SMGR_validate_get_valid_states() & SMGR_MASK_ACTIVE_READY)) { - l_error_logged = FALSE; + L_error_logged = FALSE; TRAC_IMP("SMGR: Standby to Characterization State Transition Started"); // set pstate clips @@ -253,10 +253,10 @@ errlHndl_t SMGR_standby_to_characterization() } } while (0); - if(l_errlHndl && (false == l_error_logged)) + if(l_errlHndl && (false == L_error_logged)) { - l_error_logged = TRUE; - TRAC_ERR("SMGR: Standby to Characterization Transition Failed"); + L_error_logged = TRUE; + TRAC_ERR("SMGR: Standby to Characterization Transition Failed due to not ACTIVE_READY"); /* @ * @errortype * @moduleid MAIN_STATE_TRANSITION_MID @@ -297,7 +297,6 @@ errlHndl_t SMGR_standby_to_characterization() errlHndl_t SMGR_all_to_standby() { errlHndl_t l_errlHndl = NULL; - static bool l_error_logged = FALSE; // To prevent trace and error logging over and over uint8_t wait_time = 0; int rc; @@ -373,9 +372,8 @@ errlHndl_t SMGR_all_to_standby() } while (0); - if(l_errlHndl && !l_error_logged) + if(l_errlHndl) { - l_error_logged = TRUE; TRAC_ERR("SMGR: Transition to Standby Failed"); /* @ @@ -416,7 +414,6 @@ errlHndl_t SMGR_characterization_to_observation() { errlHndl_t l_errlHndl = NULL; int rc = 0; - static bool l_error_logged = FALSE; // To prevent trace and error logging over and over Pstate l_pstate; TRAC_IMP("SMGR: Characterization to Observation Transition Started"); @@ -448,9 +445,8 @@ errlHndl_t SMGR_characterization_to_observation() } } while (0); - if(rc && !l_error_logged) + if(rc) { - l_error_logged = TRUE; TRAC_ERR("SMGR: Characterization to Observation Transition Failed"); /* @ @@ -492,7 +488,7 @@ errlHndl_t SMGR_observation_to_characterization() { int rc = 0; errlHndl_t l_errlHndl = NULL; - static bool l_error_logged = FALSE; // To prevent trace and error logging over and over + static bool L_error_logged = FALSE; // To prevent trace and error logging over and over Pstate l_pstate; TRAC_IMP("SMGR: Observation to Characterization Transition Started"); @@ -545,9 +541,9 @@ errlHndl_t SMGR_observation_to_characterization() } } while (0); - if(rc && (false == l_error_logged)) + if(rc && (false == L_error_logged)) { - l_error_logged = TRUE; + L_error_logged = TRUE; TRAC_ERR("SMGR: Observation to Characterization Transition Failed"); /* @ * @errortype @@ -588,7 +584,7 @@ errlHndl_t SMGR_observation_to_characterization() errlHndl_t SMGR_observation_to_active() { errlHndl_t l_errlHndl = NULL; - static bool l_error_logged = FALSE; // To prevent trace and error log happened over and over + static bool L_error_logged = FALSE; // To prevent trace and error log happened over and over int l_extRc = OCC_NO_EXTENDED_RC; int l_rc = 0; Pstate l_pstate; @@ -609,6 +605,7 @@ errlHndl_t SMGR_observation_to_active() if(SMGR_MASK_ACTIVE_READY == (SMGR_validate_get_valid_states() & SMGR_MASK_ACTIVE_READY)) { + TRAC_IMP("SMGR: Observation to Active Transition Started"); l_pstate = proc_freq2pstate(G_proc_fmax_mhz); l_rc = pgpe_set_clip_blocking(l_pstate); @@ -642,13 +639,13 @@ errlHndl_t SMGR_observation_to_active() // Wait for pstates enablement completition. SsxTimebase start = ssx_timebase_get(); + SsxInterval timeout = SSX_SECONDS(5); while( ! proc_is_hwpstate_enabled() ) { - SsxInterval timeout = SSX_SECONDS(5); if ((ssx_timebase_get() - start) > timeout) { l_rc = 1; - if(FALSE == l_error_logged) + if(FALSE == L_error_logged) { TRAC_ERR("SMGR: Timeout waiting for Pstates to be enabled, " "pmc_mode[%08x], chips_present[%02x], Cores Present [%08x]", @@ -659,14 +656,14 @@ errlHndl_t SMGR_observation_to_active() l_extRc = ERC_GENERIC_TIMEOUT; break; } + ssx_sleep(SSX_MICROSECONDS(10)); } // if pstates are now enabled, all conditions are already met // to transition to active state. if(proc_is_hwpstate_enabled() ) { - l_error_logged = FALSE; - TRAC_IMP("SMGR: Observation to Active Transition Started"); + L_error_logged = FALSE; // Set the RTL Flags to indicate which tasks can run // - Clear OBSERVATION b/c not in OBSERVATION State @@ -693,9 +690,9 @@ errlHndl_t SMGR_observation_to_active() TRAC_ERR("SMGR: Observation to Active Transition Failed, because pstates are not enabled"); } - if(l_rc && FALSE == l_error_logged) + if(l_rc && FALSE == L_error_logged) { - l_error_logged = TRUE; + L_error_logged = TRUE; /* @ * @errortype * @moduleid MAIN_STATE_TRANSITION_MID @@ -745,7 +742,7 @@ errlHndl_t SMGR_characterization_to_active() { int rc = 0; errlHndl_t l_errlHndl = NULL; - static bool l_error_logged = FALSE; // To prevent trace and error log happened over and over + static bool L_error_logged = FALSE; // To prevent trace and error log happened over and over do { @@ -779,7 +776,7 @@ errlHndl_t SMGR_characterization_to_active() (SMGR_validate_get_valid_states() & SMGR_MASK_ACTIVE_READY)) && proc_is_hwpstate_enabled() ) { - l_error_logged = FALSE; + L_error_logged = FALSE; TRAC_IMP("SMGR: Characterization to Active Transition Started"); // Set the RTL Flags to indicate which tasks can run @@ -794,9 +791,9 @@ errlHndl_t SMGR_characterization_to_active() } } while (0); - if(rc && (false == l_error_logged)) + if(rc && (false == L_error_logged)) { - l_error_logged = TRUE; + L_error_logged = TRUE; /* @ * @errortype * @moduleid MAIN_STATE_TRANSITION_MID diff --git a/src/occ_405/timer/timer.c b/src/occ_405/timer/timer.c index d314ae6..9695a18 100755 --- a/src/occ_405/timer/timer.c +++ b/src/occ_405/timer/timer.c @@ -83,8 +83,6 @@ bool G_wdog_enabled = false; GpeRequest G_reset_mem_deadman_request; // IPC request GPE_BUFFER(reset_mem_deadman_args_t G_gpe_reset_mem_deadman_args); // IPC args -uint32_t G_pgpe_beacon_address; // PGPE Beacon Address - //*************************************************************************/ // Function Prototypes //*************************************************************************/ @@ -131,7 +129,7 @@ void initWatchdogTimers() ERC_PPC405_WD_SETUP_FAILURE, // Extended reason code ERRL_SEV_UNRECOVERABLE, // severity NULL, // trace buffer - 0, // trace size + DEFAULT_TRACE_SIZE, //Trace Size l_rc, // userdata1 0); // userdata2 @@ -253,13 +251,12 @@ void task_poke_watchdogs(struct task * i_self) { // Examine pgpe Beacon every other call (every 4ms) //@TODO: remove when PGPE code is integrated, RTC: 163934 +#ifdef PGPE_SUPPORT if(!G_simics_environment) // PGPE Beacon is not implemented in simics { -// TODO: RTC: 163934 Enable this when PGPE beacon is enabled. -#if 0 check_pgpe_beacon(); -#endif } +#endif } // toggle pgpe beacon check flag, check only once every other call (every 4ms) @@ -479,7 +476,7 @@ void check_pgpe_beacon(void) do { // return PGPE Beacon - pgpe_beacon = in32(G_pgpe_beacon_address); + pgpe_beacon = in32(G_pgpe_header.beacon_sram_addr); // in first invocation, just initialize L_prev_pgpe_beacon // don't check if the PGPE Beacon value changed @@ -521,12 +518,18 @@ void check_pgpe_beacon(void) ERC_PGPE_BEACON_TIMEOUT, // Extended reason code ERRL_SEV_UNRECOVERABLE, // severity NULL, // trace buffer - 0, // trace size + DEFAULT_TRACE_SIZE, //Trace Size pgpe_beacon, // userdata1 - G_pgpe_beacon_address); // userdata2 + G_pgpe_header.beacon_sram_addr); // userdata2 + // TODO: RTC 170963 - re-enable reset when beacon starts working +#if 0 // Commit error log and request reset REQUEST_RESET(l_err); +#else + // Commit error log + commitErrl(&l_err); +#endif } } else diff --git a/src/occ_405/wof/wof.c b/src/occ_405/wof/wof.c index 99fd0ba..7e3d800 100644 --- a/src/occ_405/wof/wof.c +++ b/src/occ_405/wof/wof.c @@ -42,9 +42,6 @@ extern amec_sys_t g_amec_sys; extern OCCPstateParmBlock G_oppb; extern GPE_BUFFER(ipcmsg_wof_vfrt_t G_wof_vfrt_parms); extern GpeRequest G_wof_vfrt_req; -extern uint32_t G_pgpe_shared_sram_address; -extern uint32_t G_pgpe_pstate_table_address; -extern uint32_t G_pgpe_pstate_table_sz; extern uint32_t G_nest_frequency_mhz; //****************************************************************************** // Globals @@ -243,7 +240,7 @@ uint32_t calc_vfrt_mainstore_addr( void ) g_wof->vdd_step_from_start) ) + g_wof->quad_step_from_start); // Skip the wof header at the beginning of wof tables - uint32_t wof_tables_base = g_wof->vfrt_tbls_main_mem_addr + WOF_HEADER_SIZE; + uint32_t wof_tables_base = G_pgpe_header.wof_tables_addr + WOF_HEADER_SIZE; return wof_tables_base + offset; } @@ -576,7 +573,7 @@ void read_shared_sram( void ) { // Skip over the first doubleword for now (magic number and pgpe beacon) uint32_t current_pgpe_sram_addr = - G_pgpe_shared_sram_address + sizeof(uint64_t); + G_pgpe_header.shared_sram_addr + sizeof(uint64_t); // Get the actual quad states G_quad_state_0.value = in64(current_pgpe_sram_addr); @@ -639,7 +636,7 @@ void calculate_core_voltage( void ) else { // Calculate the address of the pstate for the current quad. - uint32_t pstate_addr = G_pgpe_pstate_table_address + + uint32_t pstate_addr = G_pgpe_header.occ_pstate_table_sram_addr + (g_wof->quad_x_pstates[l_quad_idx] * sizeof(OCCPstateTable_entry_t)); // Get the Pstate diff --git a/src/occ_405/wof/wof.h b/src/occ_405/wof/wof.h index 65368dd..ffe3e71 100644 --- a/src/occ_405/wof/wof.h +++ b/src/occ_405/wof/wof.h @@ -51,10 +51,14 @@ #define WOF_RC_MODE_NO_SUPPORT_MASK 0x0008 +#define WOF_MAGIC_NUMBER 0x57465448 // "WFTH" + // Structure to hold relevant data from the WOF header in Mainstore typedef struct __attribute__ ((packed)) { - uint64_t magic_number; + uint32_t magic_number; + uint8_t reserved[3]; + uint8_t version; uint8_t size_of_vfrt; uint8_t vfrt_data_size; uint8_t active_quads_start; |
