diff options
Diffstat (limited to 'src/occ_405')
| -rwxr-xr-x | src/occ_405/cent/centaur_data.c | 9 | ||||
| -rwxr-xr-x | src/occ_405/dcom/dcom.c | 5 | ||||
| -rwxr-xr-x | src/occ_405/main.c | 5 | ||||
| -rwxr-xr-x | src/occ_405/pss/apss.c | 2 |
4 files changed, 9 insertions, 12 deletions
diff --git a/src/occ_405/cent/centaur_data.c b/src/occ_405/cent/centaur_data.c index 50d4e9b..fd52a23 100755 --- a/src/occ_405/cent/centaur_data.c +++ b/src/occ_405/cent/centaur_data.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2016 */ +/* Contributors Listed Below - COPYRIGHT 2014,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -196,11 +196,10 @@ bool cent_chan_checkstop(const uint8_t i_cent) uint64_t l_data; int l_scom_rc = 0; - // Determine scom address of MCIFIR register - l_scom_addr = MCS0_MCIFIR_N(i_cent); + // TODO: RTC 163359 Centaur support + // We are unable to SCOM from the 405, so this scom was removed. + // Will need to determine how to get this information in the future. - // Do a getscom on MCIFIR register for i_cent - l_scom_rc = getscom_ffdc(l_scom_addr, &l_data, 0); if(!l_scom_rc) { //check for channel checkstop (bit 31) diff --git a/src/occ_405/dcom/dcom.c b/src/occ_405/dcom/dcom.c index d0bbf73..32f9976 100755 --- a/src/occ_405/dcom/dcom.c +++ b/src/occ_405/dcom/dcom.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2016 */ +/* Contributors Listed Below - COPYRIGHT 2011,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -112,9 +112,6 @@ void dcom_initialize_roles(void) // Locals pba_xcfg_t pbax_cfg_reg; - // Used as a debug tool to correlate time between OCCs & System Time - // getscom_ffdc(OCB_OTBR, &G_dcomTime.tod, NULL); // Commits errors internally - G_dcomTime.tod = in64(OCB_OTBR) >> 4; G_dcomTime.base = ssx_timebase_get(); pbax_cfg_reg.value = in64(PBA_XCFG); diff --git a/src/occ_405/main.c b/src/occ_405/main.c index 01f22b3..f969992 100755 --- a/src/occ_405/main.c +++ b/src/occ_405/main.c @@ -280,12 +280,13 @@ void pmc_hw_error_isr(void *private, SsxIrqId irq, int priority) * End Function Specification */ //NOTE: use "putscom pu 6B111 0 3 101 -ib -p1" to inject the error. -#define OCC_LFIR_SPARE_BIT50 0x0000000000002000ull //gm031 +#define OCC_LFIR_SPARE_BIT50 0x0000000000002000ull void occ_hw_error_isr(void *private, SsxIrqId irq, int priority) { //set bit 50 of the OCC LFIR so that the PRDF component will log an error and callout the processor //TMGT will also see a problem and log an error but it will be informational. - _putscom(OCB_OCCLFIR_OR, OCC_LFIR_SPARE_BIT50, SCOM_TIMEOUT); + + // TODO: Determine how to set this without a SCOM. //Halt occ so that hardware will enter safe mode OCC_HALT(ERRL_RC_OCC_HW_ERROR); diff --git a/src/occ_405/pss/apss.c b/src/occ_405/pss/apss.c index 71d98ef..0896184 100755 --- a/src/occ_405/pss/apss.c +++ b/src/occ_405/pss/apss.c @@ -47,7 +47,7 @@ const apssGpioConfigStruct_t G_gpio_config[2] = { {0x00, 0xFF, 0x00}, {0x00, 0xF // G_apss_mode_config: system parms needed to select correct mode command options // Configure streaming of: APSS Mode, 16 ADCs, 2 GPIOs -const apssModeConfigStruct_t G_apss_mode_config = { APSS_MODE_AUTO2, 16, 2 }; +const apssModeConfigStruct_t G_apss_mode_config = { APSS_MODE_COMPOSITE, 16, 2 }; // Power Measurements (read from APSS every RealTime loop) apssPwrMeasStruct_t G_apss_pwr_meas = { {0} }; |
