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Diffstat (limited to 'src/occ/gpe/apss_meas_read_start.pS')
| -rwxr-xr-x | src/occ/gpe/apss_meas_read_start.pS | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/src/occ/gpe/apss_meas_read_start.pS b/src/occ/gpe/apss_meas_read_start.pS new file mode 100755 index 0000000..b8cae79 --- /dev/null +++ b/src/occ/gpe/apss_meas_read_start.pS @@ -0,0 +1,144 @@ +# ***************************************************************************** +# @file apss_meas_read_start.S +# @brief Kick of the reading of power measurement from APSS +# + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section apss_meas_read_start.S APSS_MEAS_READ_START.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# @gm038 926761 milesg 05/16/2014 slowed SPI bus down from 12MHz to 10MHz on venice (8MHz on murano) +# @gs039 936836 gjsilva 08/28/2014 slowed SPI bus down from 10MHz to 8MHz on venice (~6MHz on murano) +# +# @endverbatim +# +# ***************************************************************************** + + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// + +#include <pss_constants.h> + +#define GPE_PROG_ID 0x0004 + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct G_gpe_apss_start_pwr_meas_read_args = + // { + .struct 0 +ERROR_RC: + .struct ERROR_RC + 8 +ERROR_FFDC: + .struct ERROR_FFDC + 8 + // }; + + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + +#include <gpe_macros.h> +#include <pss_macros.h> + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: GPE_apss_start_pwr_meas_read + // + // Description: Kick of the power measurement from APSS + // + // Inputs: G_gpe_apss_start_pwr_meas_read_args + // struct { + // PoreGpeErrorStruct error; + // } G_gpe_apss_start_pwr_meas_read_args + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // + // Outputs: GPE_start_pwr_meas_read (error on failure) + // + // Flow: 7/20/11 FN=GPE_apss_start_pwr_meas_read + // + // References: APSS FUnctional Specification v0.7.18 + // GPE_apss_access_scoms.odt (summary of regisers/data) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global GPE_apss_start_pwr_meas_read +GPE_apss_start_pwr_meas_read: + + // Copy passed Structure Pointer into A1 + mr A1, ETR + + // Wait for up to 5us for spi op complete, else branch to error_timeout + _wait_for_adc_ops_complete 5, error_timeout + + // Setup control regs + // frame_size=16, out_count=16, in_count=16 + ////_putscom SPIPSS_ADC_CTRL_REG0, 0x4100100000000000 + _putscom SPIPSS_ADC_CTRL_REG0, 0x4000100000000000 // Verified + // ADC FSM, clock_divider=7, frames=16 + ////_putscom SPIPSS_ADC_CTRL_REG1, 0x801FC00000000000 + ////_putscom SPIPSS_ADC_CTRL_REG1, 0x8063c00000000000 // Verified + //_putscom SPIPSS_ADC_CTRL_REG1, 0x8077c00000000000 //gm038 + _putscom SPIPSS_ADC_CTRL_REG1, 0x8093c00000000000 //@gs039 + // ADC interframe delay (5usec) + ////_putscom SPIPSS_ADC_CTRL_REG2, 0x0019000000000000 + _putscom SPIPSS_ADC_CTRL_REG2, 0x0019000000000000 // Verified + + // APSS command to continue previous command + _putscom SPIPSS_ADC_WDATA_REG, 0x0000000000000000 // Verified + + // Start SPI transaction + _putscom SPIPSS_ADC_COMMAND_REG, 0x8000000000000000 // Verified + + halt // End of GPE_apss_initialize_gpio + + +error_statusreg: + // An error/reserved bit was set when reading adc status register... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0002 + halt + + +error_timeout: + // adc_ongoing bit was never cleared after several retries... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0001 + halt + + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + + |
