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-rwxr-xr-xsrc/occ_405/cmdh/cmdh_dbug_cmd.c214
-rwxr-xr-xsrc/occ_405/cmdh/cmdh_fsp.c4
-rwxr-xr-xsrc/occ_405/cmdh/cmdh_fsp.h4
-rwxr-xr-xsrc/occ_405/cmdh/cmdh_fsp_cmds.c157
-rwxr-xr-xsrc/occ_405/homer.c7
-rwxr-xr-xsrc/occ_405/homer.h14
-rwxr-xr-xsrc/occ_405/incl/common_types.h2
-rwxr-xr-xsrc/occ_405/main.c35
-rwxr-xr-xsrc/occ_405/occ_sys_config.h3
-rwxr-xr-xsrc/occ_405/occbuildname.c2
-rwxr-xr-xsrc/occ_405/proc/proc_data.c4
-rw-r--r--src/occ_405/sensor/sensor_main_memory.c31
-rw-r--r--src/occ_405/sensor/sensor_main_memory.h30
-rwxr-xr-xsrc/occ_405/sensor/sensor_query_list.c25
14 files changed, 316 insertions, 216 deletions
diff --git a/src/occ_405/cmdh/cmdh_dbug_cmd.c b/src/occ_405/cmdh/cmdh_dbug_cmd.c
index 9f7fe72..1b752d1 100755
--- a/src/occ_405/cmdh/cmdh_dbug_cmd.c
+++ b/src/occ_405/cmdh/cmdh_dbug_cmd.c
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2018 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -73,6 +73,7 @@ extern OCCPstateParmBlock G_oppb;
//*************************************************************************/
uint16_t G_allow_trace_flags = 0x0000;
uint32_t G_internal_flags = 0x00000000;
+extern bool G_smf_mode;
// SSX Block Copy Request for copying data from HOMER to SRAM
BceRequest G_debug_pba_request;
@@ -272,129 +273,148 @@ void cmdh_dbug_peek (const cmdh_fsp_cmd_t * i_cmd_ptr,
uint8_t l_type = l_cmd_ptr->type;
uint32_t l_addr = l_cmd_ptr->address;
int l_ssxrc = SSX_OK;
+ static bool L_traced_reject = FALSE;
+ if (G_smf_mode == false)
+ {
#if PPC405_MMU_SUPPORT
- static Ppc405MmuMap L_mmuMapHomer;
- static Ppc405MmuMap L_mmuMapCommon;
+ static Ppc405MmuMap L_mmuMapHomer;
+ static Ppc405MmuMap L_mmuMapCommon;
#endif
- switch(l_type)
- {
- case 0x01: // OCI Direct Read
- // Make sure we don't overflow our response buffer
- l_len = (l_len > CMDH_FSP_RSP_DATA_SIZE ) ? CMDH_FSP_RSP_DATA_SIZE : l_len;
-
- // Read the data
- memcpy( (void *) &o_rsp_ptr->data[0],
- (void *) l_addr,
- (size_t) l_len );
- break;
-
- case 0x02: // DMA Read
- // Make sure address is 128 byte aligned required for block copy
- if(l_addr % 128)
- {
- TRAC_ERR("cmdh_dbug_peek: Address 0x%08X is not 128 byte aligned", l_addr);
- // no error handling for debug just respond with 0 bytes
- l_len = 0;
- }
- else
- {
- // only 1 length is supported by the OCC
- // ignore input length and set length to CMDH_DEBUG_DMA_READ_SIZE
- l_len = CMDH_DEBUG_DMA_READ_SIZE;
-
- // Copy data from main memory to SRAM
- // Set up a copy request
- l_ssxrc = bce_request_create(&G_debug_pba_request, // block copy object
- &G_pba_bcde_queue, // mainstore to sram copy engine
- l_addr, // mainstore address
- (uint32_t)&G_debug_dma_buffer, // sram starting address
- l_len, // size of copy
- SSX_SECONDS(1), // timeout
- NULL, // no call back
- NULL, // no call back arguments
- ASYNC_REQUEST_BLOCKING); // blocking request
-
- if(l_ssxrc != SSX_OK)
+ switch(l_type)
+ {
+ case 0x01: // OCI Direct Read
+ // Make sure we don't overflow our response buffer
+ l_len = (l_len > CMDH_FSP_RSP_DATA_SIZE ) ? CMDH_FSP_RSP_DATA_SIZE : l_len;
+
+ // Read the data
+ memcpy( (void *) &o_rsp_ptr->data[0],
+ (void *) l_addr,
+ (size_t) l_len );
+ break;
+
+ case 0x02: // DMA Read
+ // Make sure address is 128 byte aligned required for block copy
+ if(l_addr % 128)
{
- TRAC_ERR("cmdh_dbug_peek: BCDE request create failure rc=[%08X]", -l_ssxrc);
+ TRAC_ERR("cmdh_dbug_peek: Address 0x%08X is not 128 byte aligned", l_addr);
// no error handling for debug just respond with 0 bytes
l_len = 0;
}
else
{
- // Do actual copying
- l_ssxrc = bce_request_schedule(&G_debug_pba_request);
+ // only 1 length is supported by the OCC
+ // ignore input length and set length to CMDH_DEBUG_DMA_READ_SIZE
+ l_len = CMDH_DEBUG_DMA_READ_SIZE;
+
+ // Copy data from main memory to SRAM
+ // Set up a copy request
+ l_ssxrc = bce_request_create(&G_debug_pba_request, // block copy object
+ &G_pba_bcde_queue, // mainstore to sram copy engine
+ l_addr, // mainstore address
+ (uint32_t)&G_debug_dma_buffer, // sram starting address
+ l_len, // size of copy
+ SSX_SECONDS(1), // timeout
+ NULL, // no call back
+ NULL, // no call back arguments
+ ASYNC_REQUEST_BLOCKING); // blocking request
if(l_ssxrc != SSX_OK)
{
- TRAC_ERR("cmdh_dbug_peek: BCE request schedule failure rc=[%08X]", -l_ssxrc);
+ TRAC_ERR("cmdh_dbug_peek: BCDE request create failure rc=[%08X]", -l_ssxrc);
// no error handling for debug just respond with 0 bytes
l_len = 0;
}
else
{
- // Copy to response buffer
- memcpy((void *) &o_rsp_ptr->data[0],
- &G_debug_dma_buffer,
- l_len);
+ // Do actual copying
+ l_ssxrc = bce_request_schedule(&G_debug_pba_request);
+
+ if(l_ssxrc != SSX_OK)
+ {
+ TRAC_ERR("cmdh_dbug_peek: BCE request schedule failure rc=[%08X]", -l_ssxrc);
+ // no error handling for debug just respond with 0 bytes
+ l_len = 0;
+ }
+ else
+ {
+ // Copy to response buffer
+ memcpy((void *) &o_rsp_ptr->data[0],
+ &G_debug_dma_buffer,
+ l_len);
+ }
}
- }
- } // else address is 128 byte aligned
+ } // else address is 128 byte aligned
- break;
+ break;
- case 0x03: // Invalidate Cache
- //dcache_invalidate( (void *) l_addr, l_len );
- l_len = 0;
- break;
+ case 0x03: // Invalidate Cache
+ //dcache_invalidate( (void *) l_addr, l_len );
+ l_len = 0;
+ break;
- case 0x04: // Flush Cache
- dcache_flush( (void *) l_addr, l_len );
- l_len = 0;
- break;
+ case 0x04: // Flush Cache
+ dcache_flush( (void *) l_addr, l_len );
+ l_len = 0;
+ break;
#if PPC405_MMU_SUPPORT
- case 0x05: // MMU Map Mainstore
- // Map mainstore to oci space so that we can peek at it
-
- // HOMER Image
- ppc405_mmu_map(HOMER_BASE_ADDRESS, // Mainstore address (BAR0, offset 0)
- HOMER_BASE_ADDRESS, // OCI address 0x0 (BAR0)
- HOMER_SPACE_SIZE, // Size
- 0, // TLB hi flags
- 0, // TLB lo flags
- &L_mmuMapHomer); // map pointer
-
- // COMMON Image = Communal OCC Memory Map On Node
- ppc405_mmu_map(COMMON_BASE_ADDRESS, // Mainstore address (BAR2, offset 0)
- COMMON_BASE_ADDRESS, // OCI address 0xA0000000
- COMMON_SPACE_SIZE, // Size
- 0, // TLB hi flags
- 0, // TLB lo flags
- &L_mmuMapCommon); // map pointer
- l_len = 0;
- break;
- case 0x06: // MMU UnMap Mainstore
- // HOMER Image
- ppc405_mmu_unmap(&L_mmuMapHomer);
+ case 0x05: // MMU Map Mainstore
+ // Map mainstore to oci space so that we can peek at it
+
+ // HOMER Image
+ ppc405_mmu_map(HOMER_BASE_ADDRESS, // Mainstore address (BAR0, offset 0)
+ HOMER_BASE_ADDRESS, // OCI address 0x0 (BAR0)
+ HOMER_SPACE_SIZE, // Size
+ 0, // TLB hi flags
+ 0, // TLB lo flags
+ &L_mmuMapHomer); // map pointer
+
+ // COMMON Image = Communal OCC Memory Map On Node
+ ppc405_mmu_map(COMMON_BASE_ADDRESS, // Mainstore address (BAR2, offset 0)
+ COMMON_BASE_ADDRESS, // OCI address 0xA0000000
+ COMMON_SPACE_SIZE, // Size
+ 0, // TLB hi flags
+ 0, // TLB lo flags
+ &L_mmuMapCommon); // map pointer
+ l_len = 0;
+ break;
+ case 0x06: // MMU UnMap Mainstore
+ // HOMER Image
+ ppc405_mmu_unmap(&L_mmuMapHomer);
- // COMMON Image = Communal OCC Memory Map On Node
- ppc405_mmu_unmap(&L_mmuMapCommon);
+ // COMMON Image = Communal OCC Memory Map On Node
+ ppc405_mmu_unmap(&L_mmuMapCommon);
- l_len = 0;
- break;
+ l_len = 0;
+ break;
#endif
- default:
- // Didn't do anything, respond with zero bytes
- l_len = 0;
- break;
+ default:
+ // Didn't do anything, respond with zero bytes
+ l_len = 0;
+ break;
+ }
+
+ G_rsp_status = ERRL_RC_SUCCESS;
+ o_rsp_ptr->data_length[0] = CONVERT_UINT16_UINT8_HIGH(l_len);
+ o_rsp_ptr->data_length[1] = CONVERT_UINT16_UINT8_LOW(l_len);
+ }
+ else
+ {
+ if (!L_traced_reject)
+ {
+ TRAC_ERR("cmdh_dbug_peek: Peek not supported in SMF mode");
+ L_traced_reject = TRUE;
+ }
+
+ // Return error to TMGT w/no log
+ G_rsp_status = ERRL_RC_NO_SUPPORT_IN_SMF_MODE;
+ o_rsp_ptr->data_length[0] = 0;
+ o_rsp_ptr->data_length[1] = 1;
+ o_rsp_ptr->data[0] = 0x00; // no error log
}
- G_rsp_status = ERRL_RC_SUCCESS;
- o_rsp_ptr->data_length[0] = CONVERT_UINT16_UINT8_HIGH(l_len);
- o_rsp_ptr->data_length[1] = CONVERT_UINT16_UINT8_LOW(l_len);
-}
+} // end cmdh_dbug_peek()
// Function Specification
@@ -830,7 +850,7 @@ void cmdh_dbug_internal_flags( const cmdh_fsp_cmd_t * i_cmd_ptr,
}
else if ((data_length != 0) && (data_length != flag_size))
{
- TRAC_ERR("cmdh_dbug_dimm_inject: Invalid internal flags length %u (expected %u)",
+ TRAC_ERR("cmdh_dbug_internal_flags: Invalid internal flags length %u (expected %u)",
data_length, flag_size);
l_rc = ERRL_RC_INVALID_CMD_LEN;
}
diff --git a/src/occ_405/cmdh/cmdh_fsp.c b/src/occ_405/cmdh/cmdh_fsp.c
index 79d7544..1a5c288 100755
--- a/src/occ_405/cmdh/cmdh_fsp.c
+++ b/src/occ_405/cmdh/cmdh_fsp.c
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2016 */
+/* Contributors Listed Below - COPYRIGHT 2011,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -441,7 +441,7 @@ void cmdh_build_errl_rsp(const cmdh_fsp_cmd_t * i_cmd_ptr,
ERRL_USR_DTL_BINARY_DATA); //type
}
- // Fill out the response lod_id with the error id
+ // Fill out the response log_id with the error id
l_errl_rsp_ptr->log_id = getErrlLogId(*l_errlHndlPtr);
}
else
diff --git a/src/occ_405/cmdh/cmdh_fsp.h b/src/occ_405/cmdh/cmdh_fsp.h
index 7e5d4c8..d20e539 100755
--- a/src/occ_405/cmdh/cmdh_fsp.h
+++ b/src/occ_405/cmdh/cmdh_fsp.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2017 */
+/* Contributors Listed Below - COPYRIGHT 2011,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -145,6 +145,8 @@ typedef enum
ERRL_RC_INTERNAL_FAIL = 0x15,
// The OCC cannot accept the command in its present state
ERRL_RC_INVALID_STATE = 0x16,
+ // The specified command is not supported in Secure Memory Facility mode
+ ERRL_RC_NO_SUPPORT_IN_SMF_MODE = 0x17,
// This is a panic response
ERRL_RC_PANIC = 0xE0,
// This is a checkpoint response
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds.c b/src/occ_405/cmdh/cmdh_fsp_cmds.c
index cd9e352..152653c 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds.c
@@ -63,6 +63,7 @@ extern GpeRequest G_epow_gpio_detected_req;
extern opal_proc_voting_reason_t G_amec_opal_proc_throt_reason;
extern bool G_htmgt_notified_of_error;
+extern bool G_smf_mode;
// This table contains tunable parameter information that can be exposed to
// customers (only Master OCC should access/control this table)
@@ -1357,92 +1358,108 @@ errlHndl_t cmdh_amec_pass_through(const cmdh_fsp_cmd_t * i_cmd_ptr,
uint8_t l_rc = 0;
uint16_t l_rsp_data_length = CMDH_FSP_RSP_DATA_SIZE;
errl_generic_resp_t* l_err_resp_ptr = (errl_generic_resp_t*)o_rsp_ptr;
+ static bool L_traced_reject = FALSE;
- do
+ if (G_smf_mode == false)
{
-
- // Function Inputs Sanity Check
- if( (NULL == i_cmd_ptr) || (NULL == o_rsp_ptr) )
+ do
{
- l_rc = ERRL_RC_INTERNAL_FAIL;
- break;
- }
-
- // Byte0 is ipmi command number
- l_IPMImsg.u8Cmd = i_cmd_ptr->data[0];
+ // Function Inputs Sanity Check
+ if( (NULL == i_cmd_ptr) || (NULL == o_rsp_ptr) )
+ {
+ l_rc = ERRL_RC_INTERNAL_FAIL;
+ break;
+ }
- //set the ipmi command data size, byte0 and byte1 is ipmi header
- l_IPMImsg.u8CmdDataLen = CONVERT_UINT8_ARRAY_UINT16( i_cmd_ptr->data_length[0],
- i_cmd_ptr->data_length[1])
- - AMEC_AME_CMD_HEADER_SZ;
+ // Byte0 is ipmi command number
+ l_IPMImsg.u8Cmd = i_cmd_ptr->data[0];
- // Set the ipmi command data buffer
- l_IPMImsg.au8CmdData_ptr = (uint8_t *)&i_cmd_ptr->data[AMEC_AME_CMD_HEADER_SZ];
+ //set the ipmi command data size, byte0 and byte1 is ipmi header
+ l_IPMImsg.u8CmdDataLen = CONVERT_UINT8_ARRAY_UINT16( i_cmd_ptr->data_length[0],
+ i_cmd_ptr->data_length[1])
+ - AMEC_AME_CMD_HEADER_SZ;
- // Call the amester entry point
- l_rc = amester_entry_point( &l_IPMImsg,
- &l_rsp_data_length,
- o_rsp_ptr->data);
+ // Set the ipmi command data buffer
+ l_IPMImsg.au8CmdData_ptr = (uint8_t *)&i_cmd_ptr->data[AMEC_AME_CMD_HEADER_SZ];
- if(COMPCODE_NORMAL != l_rc)
- {
- TRAC_ERR("amester_entry_point failured, rc (ipmi completion code) = %d", l_rc);
+ // Call the amester entry point
+ l_rc = amester_entry_point( &l_IPMImsg,
+ &l_rsp_data_length,
+ o_rsp_ptr->data);
- // Just put the rc in the return packet and return success
- l_rsp_data_length = 1;
- o_rsp_ptr->data[0] = l_rc;
- l_rc = ERRL_RC_SUCCESS;
- }
-
- // Protect from overflowing buffer
- if(l_rsp_data_length > G_amester_max_data_length)
- {
- TRAC_ERR("amester_entry_point returned too much data. Got back %d bytes, but we only support sending %d bytes to IPMI",
- l_rsp_data_length, G_amester_max_data_length);
- /* @
- * @errortype
- * @moduleid AMEC_AMESTER_INTERFACE
- * @reasoncode INTERNAL_FAILURE
- * @userdata1 response data length
- * @userdata2 max data length
- * @userdata4 OCC_NO_EXTENDED_RC
- * @devdesc amester_entry_point returned too much data.
- */
- l_errlHndl = createErrl(
- AMEC_AMESTER_INTERFACE, //modId
- INTERNAL_FAILURE, //reasoncode
- OCC_NO_EXTENDED_RC, //Extended reason code
- ERRL_SEV_INFORMATIONAL, //Severity
- NULL, //Trace Buf
- DEFAULT_TRACE_SIZE, //Trace Size
- l_rsp_data_length, //userdata1
- G_amester_max_data_length //userdata2
- );
+ if(COMPCODE_NORMAL != l_rc)
+ {
+ TRAC_ERR("amester_entry_point failured, rc (ipmi completion code) = %d", l_rc);
- l_rc = ERRL_RC_INTERNAL_FAIL;
- break;
- }
- // Set response rc and length
- G_rsp_status = ERRL_RC_SUCCESS;
- o_rsp_ptr->data_length[0] = ((uint8_t *)&l_rsp_data_length)[0];
- o_rsp_ptr->data_length[1] = ((uint8_t *)&l_rsp_data_length)[1];
+ // Just put the rc in the return packet and return success
+ l_rsp_data_length = 1;
+ o_rsp_ptr->data[0] = l_rc;
+ l_rc = ERRL_RC_SUCCESS;
+ }
- }while(0);
+ // Protect from overflowing buffer
+ if(l_rsp_data_length > G_amester_max_data_length)
+ {
+ TRAC_ERR("amester_entry_point returned too much data. Got back %d bytes, but we only support sending %d bytes to IPMI",
+ l_rsp_data_length, G_amester_max_data_length);
+ /* @
+ * @errortype
+ * @moduleid AMEC_AMESTER_INTERFACE
+ * @reasoncode INTERNAL_FAILURE
+ * @userdata1 response data length
+ * @userdata2 max data length
+ * @userdata4 OCC_NO_EXTENDED_RC
+ * @devdesc amester_entry_point returned too much data.
+ */
+ l_errlHndl = createErrl(
+ AMEC_AMESTER_INTERFACE, //modId
+ INTERNAL_FAILURE, //reasoncode
+ OCC_NO_EXTENDED_RC, //Extended reason code
+ ERRL_SEV_INFORMATIONAL, //Severity
+ NULL, //Trace Buf
+ DEFAULT_TRACE_SIZE, //Trace Size
+ l_rsp_data_length, //userdata1
+ G_amester_max_data_length //userdata2
+ );
+
+ l_rc = ERRL_RC_INTERNAL_FAIL;
+ break;
+ }
+ // Set response rc and length
+ G_rsp_status = ERRL_RC_SUCCESS;
+ o_rsp_ptr->data_length[0] = ((uint8_t *)&l_rsp_data_length)[0];
+ o_rsp_ptr->data_length[1] = ((uint8_t *)&l_rsp_data_length)[1];
- if(l_rc)
- {
- l_err_resp_ptr->data_length[0] = 0;
- l_err_resp_ptr->data_length[1] = 1;
- G_rsp_status = l_rc;
+ }while(0);
- if(l_errlHndl)
+ if(l_rc)
{
- l_err_resp_ptr->log_id = l_errlHndl->iv_entryId;
+ l_err_resp_ptr->data_length[0] = 0;
+ l_err_resp_ptr->data_length[1] = 1;
+ G_rsp_status = l_rc;
+
+ if(l_errlHndl)
+ {
+ l_err_resp_ptr->log_id = l_errlHndl->iv_entryId;
+ }
+ else
+ {
+ l_err_resp_ptr->log_id = 0;
+ }
}
- else
+ }
+ else
+ {
+ if (!L_traced_reject)
{
- l_err_resp_ptr->log_id = 0;
+ TRAC_ERR("cmdh_amec_pass_through: Amester not supported in SMF mode");
+ L_traced_reject = TRUE;
}
+ // Return error to TMGT w/no log
+ G_rsp_status = ERRL_RC_NO_SUPPORT_IN_SMF_MODE;
+ o_rsp_ptr->data_length[0] = 0;
+ o_rsp_ptr->data_length[1] = 1;
+ o_rsp_ptr->data[0] = 0x00; // no error log
}
return l_errlHndl;
diff --git a/src/occ_405/homer.c b/src/occ_405/homer.c
index ef06fd0..adcccae 100755
--- a/src/occ_405/homer.c
+++ b/src/occ_405/homer.c
@@ -1,11 +1,11 @@
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
-/* $Source: src/occ/homer.c $ */
+/* $Source: src/occ_405/homer.c $ */
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2015 */
+/* Contributors Listed Below - COPYRIGHT 2011,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -124,6 +124,9 @@ homer_rc_t __attribute__((optimize("O1"))) homer_hd_map_read_unmap(const homer_r
case HOMER_FIR_PARMS:
memcpy(o_host_data, &(l_hdcfg_data->firParms[0]), HOMER_FIR_PARM_SIZE);
break;
+ case HOMER_SMF_MODE:
+ *(uint32_t *)o_host_data = l_hdcfg_data->smfMode;
+ break;
default:
l_rc = HOMER_UNKNOWN_ID;
break;
diff --git a/src/occ_405/homer.h b/src/occ_405/homer.h
index 6961a32..25473e5 100755
--- a/src/occ_405/homer.h
+++ b/src/occ_405/homer.h
@@ -1,11 +1,11 @@
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
-/* $Source: src/occ/homer.h $ */
+/* $Source: src/occ_405/homer.h $ */
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2015 */
+/* Contributors Listed Below - COPYRIGHT 2011,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -77,6 +77,12 @@ enum fir_master
FIR_OCC_IS_FIR_MASTER = 0x00000001
};
+enum smf_mode_e
+{
+ SMF_MODE_NOT_ENABLED = 0x00000000,
+ SMF_MODE_ENABLED = 0x00000001
+};
+
// Version(s) of HOMER host data currently supported
typedef enum homer_version
{
@@ -91,6 +97,7 @@ typedef enum homer_read_var
HOMER_INT_TYPE,
HOMER_FIR_MASTER,
HOMER_FIR_PARMS,
+ HOMER_SMF_MODE,
HOMER_LAST_VAR
} homer_read_var_t;
@@ -114,7 +121,8 @@ struct occHostConfigDataArea
uint32_t occInterruptType;
uint32_t firMaster;
uint8_t firParms[HOMER_FIR_PARM_SIZE];
- uint8_t __reserved[HOMER_HD_SZ - (4 * sizeof(uint32_t)) - HOMER_FIR_PARM_SIZE];
+ uint32_t smfMode;
+ uint8_t __reserved[HOMER_HD_SZ - (5 * sizeof(uint32_t)) - HOMER_FIR_PARM_SIZE];
}__attribute__ ((__packed__));
typedef struct occHostConfigDataArea occHostConfigDataArea_t;
diff --git a/src/occ_405/incl/common_types.h b/src/occ_405/incl/common_types.h
index f932adf..273d50f 100755
--- a/src/occ_405/incl/common_types.h
+++ b/src/occ_405/incl/common_types.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2018 */
+/* Contributors Listed Below - COPYRIGHT 2011,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index ad2f791..f0cb738 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -106,6 +106,7 @@ extern uint32_t G_khz_per_pstate;
extern uint8_t G_proc_pmin;
extern uint8_t G_proc_pmax;
+extern bool G_smf_mode;
extern PWR_READING_TYPE G_pwr_reading_type;
@@ -2091,10 +2092,10 @@ int main(int argc, char **argv)
{
// Trace what happened before ssx initialization
MAIN_TRAC_INFO("HOMER accessed, rc=%d, version=%d, ssx_rc=%d",
- l_homerrc, l_homer_version, l_ssxrc);
+ l_homerrc, l_homer_version, l_ssxrc);
MAIN_TRAC_INFO("HOMER accessed, rc=%d, nest_freq=%d, ssx_rc=%d",
- l_homerrc2, l_tb_freq_hz, l_ssxrc2);
+ l_homerrc2, l_tb_freq_hz, l_ssxrc2);
// Handle any errors from the version access
homer_log_access_error(l_homerrc,
@@ -2155,7 +2156,7 @@ int main(int argc, char **argv)
}
TRAC_IMP("HOMER accessed, rc=%d, FIR master=%d, ssx_rc=%d",
- l_homerrc, l_fir_master, l_ssxrc);
+ l_homerrc, l_fir_master, l_ssxrc);
// Handle any errors from the FIR master access
homer_log_access_error(l_homerrc,
@@ -2171,13 +2172,39 @@ int main(int argc, char **argv)
&l_ssxrc);
TRAC_IMP("HOMER accessed, rc=%d, FIR parms buffer 0x%x, ssx_rc=%d",
- l_homerrc, &G_fir_data_parms[0], l_ssxrc);
+ l_homerrc, &G_fir_data_parms[0], l_ssxrc);
// Handle any errors from the FIR master access
homer_log_access_error(l_homerrc,
l_ssxrc,
(uint32_t)&G_fir_data_parms[0]);
}
+
+
+ // Get the SMF mode indicator
+ uint32_t l_smf_mode = SMF_MODE_NOT_ENABLED;
+ l_homerrc = homer_hd_map_read_unmap(HOMER_SMF_MODE,
+ &l_smf_mode,
+ &l_ssxrc);
+
+ if (((HOMER_SUCCESS == l_homerrc) || (HOMER_SSX_UNMAP_ERR == l_homerrc)) &&
+ (SMF_MODE_ENABLED == l_smf_mode))
+ {
+ G_smf_mode = true;
+ }
+ else
+ {
+ G_smf_mode = false;
+ }
+
+ TRAC_IMP("HOMER accessed, rc=%d, SMF mode=%d, ssx_rc=%d",
+ l_homerrc, l_smf_mode, l_ssxrc);
+
+ // Handle any errors
+ homer_log_access_error(l_homerrc,
+ l_ssxrc,
+ l_smf_mode);
+
}//G_ipl_time
else
{
diff --git a/src/occ_405/occ_sys_config.h b/src/occ_405/occ_sys_config.h
index ff685a2..d1a9269 100755
--- a/src/occ_405/occ_sys_config.h
+++ b/src/occ_405/occ_sys_config.h
@@ -81,8 +81,7 @@ typedef union
struct
{
uint8_t kvm: 1;
- uint8_t smf: 1;
- uint8_t reserved: 2;
+ uint8_t reserved: 3;
uint8_t report_dvfs_nom: 1;
uint8_t reserved_2: 1;
uint8_t non_redund_ps: 1;
diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c
index 5cafbd6..1f73927 100755
--- a/src/occ_405/occbuildname.c
+++ b/src/occ_405/occbuildname.c
@@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) =
#else
-volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_190402a\0" /*</BuildName>*/ ;
+volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_190424a\0" /*</BuildName>*/ ;
#endif
diff --git a/src/occ_405/proc/proc_data.c b/src/occ_405/proc/proc_data.c
index 88c179f..0c82711 100755
--- a/src/occ_405/proc/proc_data.c
+++ b/src/occ_405/proc/proc_data.c
@@ -110,6 +110,8 @@ void print_core_data_sensors(uint8_t core);
void print_core_status(uint8_t core);
#endif
+extern bool G_smf_mode;
+
// Function Specification
//
// Name: task_core_data
@@ -718,7 +720,7 @@ void task_24x7(task_t * i_task)
static bool L_logged_disable = FALSE;
// Schedule 24x7 task if it hasn't been disabled
- if( (!G_24x7_disabled) && !(G_internal_flags & INT_FLAG_DISABLE_24X7) )
+ if( (!G_24x7_disabled) && !(G_internal_flags & INT_FLAG_DISABLE_24X7))
{
// Schedule 24x7 task if idle
if (!async_request_is_idle(&G_24x7_request.request))
diff --git a/src/occ_405/sensor/sensor_main_memory.c b/src/occ_405/sensor/sensor_main_memory.c
index 458c2dc..c0abbe2 100644
--- a/src/occ_405/sensor/sensor_main_memory.c
+++ b/src/occ_405/sensor/sensor_main_memory.c
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2017,2018 */
+/* Contributors Listed Below - COPYRIGHT 2017,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -52,19 +52,6 @@
// Main Memory Sensors - Private Defines/Structs/Globals
//******************************************************************************/
-/**
- * Main memory sensor struct. Represents one OCC sensor that should be copied
- * to main memory. Uses bit fields to reduce memory usage.
- */
-typedef struct __attribute__ ((packed))
-{
- uint16_t gsid; ///< Global Sensor ID
- uint8_t smf_mode : 1; ///< Is sensor copied when SMF mode enabled?
- uint8_t master_only : 1; ///< Is sensor only available from master OCC?
- uint8_t valid : 1; ///< Is sensor valid (able to be copied)?
- uint8_t enabled : 1; ///< Is sensor enabled (chosen to be copied)?
- uint8_t struct_ver : 2; ///< See MM_SENSOR_NAMES_STRUCT_VERSION_VALUES
-} main_mem_sensor_t;
/**
* Macro to build one main_mem_sensor_t instance.
@@ -242,14 +229,6 @@ main_mem_sensor_t G_main_mem_sensors[] =
MAIN_MEM_MEMORY_SENSORS (MEMSPM, false, false),
};
-/**
- * Number of main memory sensors (in G_main_mem_sensors).
- *
- * Note that some sensors might not be valid or enabled, and as a result they
- * will not be copied to main memory.
- */
-#define MAIN_MEM_SENSOR_COUNT (sizeof(G_main_mem_sensors) / sizeof(G_main_mem_sensors[0]))
-
/*
* Check if Sensor Names Block is too small to hold all of the main memory
* sensors. If so generate a compile-time error.
@@ -455,14 +434,12 @@ uint32_t G_mm_sensor_readings_buf_addr;
//******************************************************************************
-// Public Globals
+// Public Globals (see description in header file)
//******************************************************************************
-// See description in header file
bool G_main_mem_sensors_initialized = false;
-// See description in header file
-bool G_main_mem_sensors_smf_mode_enabled = false;
+bool G_smf_mode = false;
//******************************************************************************
@@ -486,7 +463,7 @@ void mm_sensors_init_internals(void)
main_mem_sensor_t * l_mm_sensor = &G_main_mem_sensors[l_index];
// Set valid field based on SMF mode and OCC role
- if (G_main_mem_sensors_smf_mode_enabled && !l_mm_sensor->smf_mode)
+ if (G_smf_mode && !l_mm_sensor->smf_mode)
{
// SMF mode is enabled and sensor is not copied when in SMF mode
l_mm_sensor->valid = false;
diff --git a/src/occ_405/sensor/sensor_main_memory.h b/src/occ_405/sensor/sensor_main_memory.h
index f989e13..8befbb0 100644
--- a/src/occ_405/sensor/sensor_main_memory.h
+++ b/src/occ_405/sensor/sensor_main_memory.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2017,2017 */
+/* Contributors Listed Below - COPYRIGHT 2017,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -60,7 +60,7 @@
* These buffers contain the dynamic sensor data, such as the current sample,
* timestamp, and maximum value. The OCC alternates between the two buffers so
* that one buffer is always complete and readable by OPAL.
- *
+ *
* For more information see the OCC Firmware Interface Specification document.
*/
@@ -235,6 +235,20 @@ typedef struct __attribute__ ((packed))
sizeof(mm_sensor_readings_full_t) : \
sizeof(mm_sensor_readings_counter_t))
+/**
+ * Main memory sensor struct. Represents one OCC sensor that should be copied
+ * to main memory. Uses bit fields to reduce memory usage.
+ */
+typedef struct __attribute__ ((packed))
+{
+ uint16_t gsid; ///< Global Sensor ID
+ uint8_t smf_mode : 1; ///< Is sensor copied when SMF mode enabled?
+ uint8_t master_only : 1; ///< Is sensor only available from master OCC?
+ uint8_t valid : 1; ///< Is sensor valid (able to be copied)?
+ uint8_t enabled : 1; ///< Is sensor enabled (chosen to be copied)?
+ uint8_t struct_ver : 2; ///< See MM_SENSOR_NAMES_STRUCT_VERSION_VALUES
+} main_mem_sensor_t;
+
//******************************************************************************
// Globals
@@ -251,7 +265,17 @@ extern bool G_main_mem_sensors_initialized;
* enabled only a subset of sensors will be copied to main memory. Default
* value is false (not enabled).
*/
-extern bool G_main_mem_sensors_smf_mode_enabled;
+extern bool G_smf_mode;
+
+extern main_mem_sensor_t G_main_mem_sensors[337];
+
+/**
+ * Number of main memory sensors (in G_main_mem_sensors).
+ *
+ * Note that some sensors might not be valid or enabled, and as a result they
+ * will not be copied to main memory.
+ */
+#define MAIN_MEM_SENSOR_COUNT (sizeof(G_main_mem_sensors) / sizeof(G_main_mem_sensors[0]))
//******************************************************************************
diff --git a/src/occ_405/sensor/sensor_query_list.c b/src/occ_405/sensor/sensor_query_list.c
index 2cae2c7..3ac38d0 100755
--- a/src/occ_405/sensor/sensor_query_list.c
+++ b/src/occ_405/sensor/sensor_query_list.c
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -34,7 +34,8 @@
#include <sensor_service_codes.h> // sensor module ids
#include <occ_service_codes.h> // sensor module ids
#include <sensor.h> // For Sensor defines
-#include <sensor_query_list.h> // For args to command
+#include <sensor_query_list.h> // For args to command
+#include <sensor_main_memory.h>
//*************************************************************************/
// Externs
@@ -55,6 +56,7 @@
//*************************************************************************/
// Globals
//*************************************************************************/
+extern bool G_smf_mode;
//*************************************************************************/
// Function Prototypes
@@ -228,6 +230,25 @@ errlHndl_t querySensorList(const querySensorListArg_t * i_argPtr)
continue;
}
+ if (G_smf_mode)
+ {
+ // Prevent adding sensors that are not supported in SMF mode
+ uint16_t l_index;
+ bool l_skip = FALSE;
+ for (l_index = 0; l_index < MAIN_MEM_SENSOR_COUNT; ++l_index)
+ {
+ if (G_main_mem_sensors[l_index].gsid == l_cnt)
+ {
+ if (G_main_mem_sensors[l_index].smf_mode == 0)
+ {
+ l_skip = TRUE;
+ }
+ break;
+ }
+ }
+ if (l_skip) continue;
+ }
+
if (o_sensors != NULL)
{
// All conditions match. Include current sensor in the query list
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