diff options
| -rwxr-xr-x | src/occ/cmdh/cmdh_fsp.c | 10 | ||||
| -rwxr-xr-x | src/occ/errl/errl.c | 17 | ||||
| -rwxr-xr-x | src/occ/incl/occ_common.h | 1 | ||||
| -rwxr-xr-x | src/ssx/pgp/registers/ocb_firmware_registers.h | 6 |
4 files changed, 29 insertions, 5 deletions
diff --git a/src/occ/cmdh/cmdh_fsp.c b/src/occ/cmdh/cmdh_fsp.c index 7c39e75..e80e518 100755 --- a/src/occ/cmdh/cmdh_fsp.c +++ b/src/occ/cmdh/cmdh_fsp.c @@ -512,9 +512,17 @@ errlHndl_t cmdh_fsp_init(void) }while(0); } } + else if(G_occ_interrupt_type == PSIHB_INTERRUPT) + { + // For systems like Habanero, OCC will use the PSIHB complex to + // send an interrupt to Host. This is done via a simple SCOM + // register, so there is nothing to initialize here. + } else { - // TODO: For Phas 4 of Habanero, need to init this path + // Invalid interrupt type + TRAC_ERR("cmdh_fsp_init: Invalid OCC interrupt type was detected! interrupt_type[%d]", + G_occ_interrupt_type); } return l_errlHndl; diff --git a/src/occ/errl/errl.c b/src/occ/errl/errl.c index f113fc1..8867900 100755 --- a/src/occ/errl/errl.c +++ b/src/occ/errl/errl.c @@ -58,6 +58,8 @@ errlHndl_t G_occErrSlots[ERRL_MAX_SLOTS] = { (errlHndl_t) G_callslot }; +extern uint8_t G_occ_interrupt_type; + void hexDumpLog( errlHndl_t i_log ); // Function Specification @@ -508,6 +510,8 @@ void addTraceToErrl( // End Function Specification void reportErrorLog( errlHndl_t i_err, uint16_t i_entrySize ) { + ocb_occmisc_t l_reg; + // report the log // will need to give them the address and size to read @@ -517,8 +521,17 @@ void reportErrorLog( errlHndl_t i_err, uint16_t i_entrySize ) i_err->iv_userDetails.iv_modId, i_err->iv_reasonCode, i_err->iv_userDetails.iv_userData1, i_err->iv_userDetails.iv_userData2); - // TODO: remove this when tracing is enabled - hexDumpLog( i_err ); + // If this system is using PSIHB complex, send an interrupt to Host so that + // Host can inform HTMGT to collect the error log + if (G_occ_interrupt_type == PSIHB_INTERRUPT) + { + // From OCC OpenPower Interface v1.1, OCC needs to set bits 0 and 1 of + // the OCB_OCCMISC register + l_reg.fields.core_ext_intr = 1; + l_reg.fields.reason_intr = 1; + + out32(OCB_OCCMISC_OR, l_reg.value); + } } diff --git a/src/occ/incl/occ_common.h b/src/occ/incl/occ_common.h index dab5205..0c28f89 100755 --- a/src/occ/incl/occ_common.h +++ b/src/occ/incl/occ_common.h @@ -269,6 +269,7 @@ enum //Used by G_occ_interrupt_type to distinguish between FSP supported OCCs and other servers. #define FSP_SUPPORTED_OCC 0x00 +#define PSIHB_INTERRUPT 0x01 // TRAP instruction should also set FIR bits along with halting PPC405 // Set DBCR0 to initial value (setting external debug event) so that diff --git a/src/ssx/pgp/registers/ocb_firmware_registers.h b/src/ssx/pgp/registers/ocb_firmware_registers.h index 4a4ddb2..fe5348b 100755 --- a/src/ssx/pgp/registers/ocb_firmware_registers.h +++ b/src/ssx/pgp/registers/ocb_firmware_registers.h @@ -1143,9 +1143,11 @@ typedef union ocb_occmisc { struct { #ifdef _BIG_ENDIAN uint32_t core_ext_intr : 1; - uint32_t _reserved0 : 31; + uint32_t reason_intr : 1; + uint32_t _reserved0 : 30; #else - uint32_t _reserved0 : 31; + uint32_t _reserved0 : 30; + uint32_t reason_intr : 1; uint32_t core_ext_intr : 1; #endif // _BIG_ENDIAN } fields; |
